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nv50: primitive display interrupt handler.

main
Maarten Maathuis 2008-04-03 01:13:31 +02:00
parent 562f95ea96
commit 3fc444a5e8
2 changed files with 17 additions and 0 deletions
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13
shared-core/nouveau_irq.c
View File

@ -446,6 +446,14 @@ nouveau_crtc_irq_handler(struct drm_device *dev, int crtc)
}
}
static void
nouveau_nv50_display_irq_handler(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
NV_WRITE(NV50_DISPLAY_SUPERVISOR, NV_READ(NV50_DISPLAY_SUPERVISOR));
}
irqreturn_t
nouveau_irq_handler(DRM_IRQ_ARGS)
{
@ -472,6 +480,11 @@ nouveau_irq_handler(DRM_IRQ_ARGS)
status &= ~NV_PMC_INTR_0_CRTCn_PENDING;
}
if (status & NV_PMC_INTR_0_NV50_DISPLAY_PENDING) {
nouveau_nv50_display_irq_handler(dev);
status &= ~NV_PMC_INTR_0_NV50_DISPLAY_PENDING;
}
if (status)
DRM_ERROR("Unhandled PMC INTR status bits 0x%08x\n", status);

4
shared-core/nouveau_reg.h
View File

@ -87,6 +87,7 @@
# define NV_PMC_INTR_0_PGRAPH_PENDING (1<<12)
# define NV_PMC_INTR_0_CRTC0_PENDING (1<<24)
# define NV_PMC_INTR_0_CRTC1_PENDING (1<<25)
# define NV_PMC_INTR_0_NV50_DISPLAY_PENDING (1<<26)
# define NV_PMC_INTR_0_CRTCn_PENDING (3<<24)
#define NV03_PMC_INTR_EN_0 0x00000140
# define NV_PMC_INTR_EN_0_MASTER_ENABLE (1<< 0)
@ -535,6 +536,9 @@
#define NV_CRTC1_INTEN 0x00602140
# define NV_CRTC_INTR_VBLANK (1<<0)
/* This name is a partial guess. */
#define NV50_DISPLAY_SUPERVISOR 0x00610024
/* Fifo commands. These are not regs, neither masks */
#define NV03_FIFO_CMD_JUMP 0x20000000
#define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc