Replace U(8|16) with u(8|16).
parent
ec7730e5ba
commit
406ded3816
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@ -96,7 +96,7 @@
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struct xgi_aperture {
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U32 base; // pcie base is different from fb base
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U32 size;
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U8 *vbase;
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u8 *vbase;
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};
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struct xgi_screen_info {
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@ -120,7 +120,7 @@ struct xgi_info {
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int slot;
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int vendor_id;
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U32 device_id;
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U8 revision_id;
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u8 revision_id;
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/* physical characteristics */
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struct xgi_aperture mmio;
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@ -113,7 +113,7 @@ static U32 s_invalid_begin = 0;
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bool xgi_ge_irq_handler(struct xgi_info * info)
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{
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volatile U8 *mmio_vbase = info->mmio.vbase;
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volatile u8 *mmio_vbase = info->mmio.vbase;
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volatile U32 *ge_3d_status = (volatile U32 *)(mmio_vbase + 0x2800);
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U32 int_status = ge_3d_status[4]; // interrupt status
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U32 auto_reset_count = 0;
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@ -135,11 +135,11 @@ bool xgi_ge_irq_handler(struct xgi_info * info)
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static U32 continoue_int_count = 0;
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// OE II is busy.
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while (old_ge_status & 0x001c0000) {
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U16 check;
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u16 check;
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// Check Read back status
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*(mmio_vbase + 0x235c) = 0x80;
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check =
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*((volatile U16 *)(mmio_vbase +
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*((volatile u16 *)(mmio_vbase +
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0x2360));
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if ((check & 0x3f) !=
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((check & 0x3f00) >> 8)) {
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@ -149,7 +149,7 @@ bool xgi_ge_irq_handler(struct xgi_info * info)
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// Check RO channel
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*(mmio_vbase + 0x235c) = 0x83;
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check =
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*((volatile U16 *)(mmio_vbase +
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*((volatile u16 *)(mmio_vbase +
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0x2360));
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if ((check & 0x0f) !=
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((check & 0xf0) >> 4)) {
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@ -159,7 +159,7 @@ bool xgi_ge_irq_handler(struct xgi_info * info)
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// Check RW channel
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*(mmio_vbase + 0x235c) = 0x88;
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check =
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*((volatile U16 *)(mmio_vbase +
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*((volatile u16 *)(mmio_vbase +
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0x2360));
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if ((check & 0x0f) !=
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((check & 0xf0) >> 4)) {
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@ -169,7 +169,7 @@ bool xgi_ge_irq_handler(struct xgi_info * info)
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// Check RO channel outstanding
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*(mmio_vbase + 0x235c) = 0x8f;
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check =
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*((volatile U16 *)(mmio_vbase +
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*((volatile u16 *)(mmio_vbase +
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0x2360));
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if (0 != (check & 0x3ff)) {
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is_wrong_signal = TRUE;
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@ -178,7 +178,7 @@ bool xgi_ge_irq_handler(struct xgi_info * info)
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// Check RW channel outstanding
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*(mmio_vbase + 0x235c) = 0x90;
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check =
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*((volatile U16 *)(mmio_vbase +
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*((volatile u16 *)(mmio_vbase +
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0x2360));
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if (0 != (check & 0x3ff)) {
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is_wrong_signal = TRUE;
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@ -216,10 +216,10 @@ bool xgi_ge_irq_handler(struct xgi_info * info)
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((--time_out) &
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0xfff)) ;
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if (0 == time_out) {
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U8 old_3ce;
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U8 old_3cf;
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U8 old_index;
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U8 old_36;
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u8 old_3ce;
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u8 old_3cf;
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u8 old_index;
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u8 old_36;
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XGI_INFO
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("Can not reset back 0x%lx!\n",
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@ -290,12 +290,12 @@ bool xgi_ge_irq_handler(struct xgi_info * info)
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bool xgi_crt_irq_handler(struct xgi_info * info)
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{
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bool ret = FALSE;
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U8 save_3ce = bReadReg(0x3ce);
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u8 save_3ce = bReadReg(0x3ce);
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if (bIn3cf(0x37) & 0x01) // CRT1 interrupt just happened
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{
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U8 op3cf_3d;
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U8 op3cf_37;
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u8 op3cf_3d;
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u8 op3cf_37;
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// What happened?
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op3cf_37 = bIn3cf(0x37);
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@ -314,14 +314,14 @@ bool xgi_crt_irq_handler(struct xgi_info * info)
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bool xgi_dvi_irq_handler(struct xgi_info * info)
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{
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bool ret = FALSE;
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U8 save_3ce = bReadReg(0x3ce);
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u8 save_3ce = bReadReg(0x3ce);
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if (bIn3cf(0x38) & 0x20) // DVI interrupt just happened
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{
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U8 op3cf_39;
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U8 op3cf_37;
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U8 op3x5_5a;
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U8 save_3x4 = bReadReg(0x3d4);;
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u8 op3cf_39;
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u8 op3cf_37;
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u8 op3x5_5a;
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u8 save_3x4 = bReadReg(0x3d4);;
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// What happened?
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op3cf_37 = bIn3cf(0x37);
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@ -33,8 +33,6 @@
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* Typedefs *
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***************************************************************************/
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typedef unsigned char U8; /* 0 to 255 */
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typedef unsigned short U16; /* 0 to 65535 */
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/*
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* mainly for 64-bit linux, where long is 64 bits
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* and win9x, where int is 16 bit.
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