replace magic number with macro constant RADEON_ZBLOCK16
parent
310abb39b2
commit
408376b203
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@ -1336,7 +1336,8 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
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*/
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dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
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(dev_priv->color_fmt << 10) |
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(1 << 15));
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(dev_priv->microcode_version == UCODE_R100 ?
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RADEON_ZBLOCK16 : 0));
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dev_priv->depth_clear.rb3d_zstencilcntl =
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(dev_priv->depth_fmt |
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@ -468,6 +468,7 @@ extern void radeon_driver_free_filp_priv(drm_device_t * dev,
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# define RADEON_ROP_ENABLE (1 << 6)
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# define RADEON_STENCIL_ENABLE (1 << 7)
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# define RADEON_Z_ENABLE (1 << 8)
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# define RADEON_ZBLOCK16 (1 << 15)
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#define RADEON_RB3D_DEPTHOFFSET 0x1c24
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#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
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#define RADEON_RB3D_DEPTHPITCH 0x1c28
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@ -999,7 +999,6 @@ static void radeon_cp_dispatch_clear(drm_device_t * dev,
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tempRE_CNTL = 0;
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tempRB3D_CNTL = depth_clear->rb3d_cntl;
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tempRB3D_CNTL &= ~(1 << 15); /* unset radeon magic flag */
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tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
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tempRB3D_STENCILREFMASK = 0x0;
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@ -1343,7 +1343,8 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
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*/
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dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
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(dev_priv->color_fmt << 10) |
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(1<<15));
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(dev_priv->microcode_version == UCODE_R100 ?
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RADEON_ZBLOCK16 : 0));
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dev_priv->depth_clear.rb3d_zstencilcntl =
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(dev_priv->depth_fmt |
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@ -411,6 +411,7 @@ extern void radeon_driver_irq_uninstall( drm_device_t *dev );
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# define RADEON_ROP_ENABLE (1 << 6)
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# define RADEON_STENCIL_ENABLE (1 << 7)
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# define RADEON_Z_ENABLE (1 << 8)
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# define RADEON_ZBLOCK16 (1 << 15)
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#define RADEON_RB3D_DEPTHOFFSET 0x1c24
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#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
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#define RADEON_RB3D_DEPTHPITCH 0x1c28
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@ -953,7 +953,6 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
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tempRE_CNTL = 0;
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tempRB3D_CNTL = depth_clear->rb3d_cntl;
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tempRB3D_CNTL &= ~(1<<15); /* unset radeon magic flag */
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tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
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tempRB3D_STENCILREFMASK = 0x0;
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