set the base address of the CRTC correctly
parent
65f465ed5a
commit
40bd6dcd86
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@ -351,9 +351,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y)
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int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE);
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int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE);
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int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
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int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
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Start = crtc->fb->offset;
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Start = crtc->fb->offset + dev_priv->baseaddr;
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Offset = ((y * crtc->fb->width + x) * (crtc->fb->bits_per_pixel / 8));
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Offset = ((y * crtc->fb->width + x) * (crtc->fb->bits_per_pixel / 8));
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DRM_DEBUG("Writing base %08X %08X %d %d\n", Start, Offset, x, y);
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if (IS_I965G(dev)) {
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if (IS_I965G(dev)) {
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I915_WRITE(dspbase, Offset);
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I915_WRITE(dspbase, Offset);
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I915_READ(dspbase);
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I915_READ(dspbase);
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@ -877,11 +877,13 @@ int i915_driver_load(drm_device_t *dev, unsigned long flags)
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if (IS_I9XX(dev)) {
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if (IS_I9XX(dev)) {
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dev_priv->mmiobase = drm_get_resource_start(dev, 0);
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dev_priv->mmiobase = drm_get_resource_start(dev, 0);
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dev_priv->mmiolen = drm_get_resource_len(dev, 0);
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dev_priv->mmiolen = drm_get_resource_len(dev, 0);
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dev_priv->baseaddr = drm_get_resource_start(dev, 2) & 0xff000000;
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} else if (drm_get_resource_start(dev, 1)) {
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} else if (drm_get_resource_start(dev, 1)) {
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dev_priv->mmiobase = drm_get_resource_start(dev, 1);
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dev_priv->mmiobase = drm_get_resource_start(dev, 1);
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dev_priv->mmiolen = drm_get_resource_len(dev, 1);
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dev_priv->mmiolen = drm_get_resource_len(dev, 1);
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dev_priv->baseaddr = drm_get_resource_start(dev, 0) & 0xff000000;
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} else {
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} else {
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DRM_ERROR("Unable to find MMIO registers\n");
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DRM_ERROR("Unable to find MMIO registers or FB\n");
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return -ENODEV;
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return -ENODEV;
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}
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}
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@ -92,6 +92,7 @@ typedef struct drm_i915_private {
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drm_local_map_t *sarea;
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drm_local_map_t *sarea;
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drm_local_map_t *mmio_map;
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drm_local_map_t *mmio_map;
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unsigned long baseaddr;
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unsigned long mmiobase;
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unsigned long mmiobase;
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unsigned long mmiolen;
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unsigned long mmiolen;
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