complete PCIE backend for ttm
ttm test runs with it at least, needs to do more testing on itmain
parent
234a906200
commit
4294dcc050
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@ -51,6 +51,27 @@ static __inline__ void insert_page_into_table(struct ati_pcigart_info *info, u32
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}
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}
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static __inline__ u32 get_page_base_from_table(struct ati_pcigart_info *info, u32 *pci_gart)
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{
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u32 retval;
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switch(info->gart_reg_if) {
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case DRM_ATI_GART_IGP:
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retval = *pci_gart;
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retval &= ~0xc;
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break;
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case DRM_ATI_GART_PCIE:
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retval = *pci_gart;
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retval &= ~0xc;
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retval <<= 8;
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break;
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default:
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case DRM_ATI_GART_PCI:
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retval = *pci_gart;
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break;
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}
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return retval;
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}
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static void *drm_ati_alloc_pcigart_table(int order)
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@ -258,9 +279,10 @@ static int ati_pcigart_populate(drm_ttm_backend_t *backend,
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ati_pcigart_ttm_backend_t *atipci_be =
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container_of(backend, ati_pcigart_ttm_backend_t, backend);
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DRM_DEBUG("%d\n", num_pages);
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DRM_ERROR("%ld\n", num_pages);
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atipci_be->pages = pages;
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atipci_be->num_pages = num_pages;
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atipci_be->populated = 1;
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return 0;
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}
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@ -271,28 +293,58 @@ static int ati_pcigart_bind_ttm(drm_ttm_backend_t *backend,
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ati_pcigart_ttm_backend_t *atipci_be =
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container_of(backend, ati_pcigart_ttm_backend_t, backend);
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off_t j;
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int i;
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struct ati_pcigart_info *info = atipci_be->gart_info;
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u32 *pci_gart;
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u32 page_base;
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pci_gart = info->addr;
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DRM_ERROR("Offset is %08lX\n", offset);
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j = offset;
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while (j < (offset + atipci_be->num_pages)) {
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if (get_page_base_from_table(info, pci_gart+j))
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return -EBUSY;
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j++;
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}
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// for (i = 0, j = offset; i < mem->page_count; i++, j++) {
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for (i = 0, j = offset; i < atipci_be->num_pages; i++, j++) {
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struct page *cur_page = atipci_be->pages[i];
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/* write value */
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// }
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page_base = page_to_phys(cur_page);
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insert_page_into_table(info, page_base, pci_gart + j);
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}
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atipci_be->gart_flush_fn(atipci_be->dev);
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atipci_be->bound = 1;
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atipci_be->offset = offset;
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/* need to traverse table and add entries */
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DRM_DEBUG("\n");
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return -1;
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return 0;
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}
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static int ati_pcigart_unbind_ttm(drm_ttm_backend_t *backend)
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{
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ati_pcigart_ttm_backend_t *atipci_be =
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container_of(backend, ati_pcigart_ttm_backend_t, backend);
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struct ati_pcigart_info *info = atipci_be->gart_info;
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unsigned long offset = atipci_be->offset;
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int i;
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off_t j;
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u32 *pci_gart = info->addr;
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DRM_DEBUG("\n");
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return -1;
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if (atipci_be->bound != 1)
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return -EINVAL;
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for (i = 0, j = offset; i < atipci_be->num_pages; i++, j++) {
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*(pci_gart + j) = 0;
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}
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atipci_be->gart_flush_fn(atipci_be->dev);
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atipci_be->bound = 0;
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atipci_be->offset = 0;
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return 0;
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}
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static void ati_pcigart_clear_ttm(drm_ttm_backend_t *backend)
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@ -334,7 +386,7 @@ static drm_ttm_backend_func_t ati_pcigart_ttm_backend =
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.destroy = ati_pcigart_destroy_ttm,
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};
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drm_ttm_backend_t *ati_pcigart_init_ttm(struct drm_device *dev, struct ati_pcigart_info *info)
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drm_ttm_backend_t *ati_pcigart_init_ttm(struct drm_device *dev, struct ati_pcigart_info *info, void (*gart_flush_fn)(struct drm_device *dev))
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{
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ati_pcigart_ttm_backend_t *atipci_be;
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@ -346,6 +398,8 @@ drm_ttm_backend_t *ati_pcigart_init_ttm(struct drm_device *dev, struct ati_pciga
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atipci_be->backend.func = &ati_pcigart_ttm_backend;
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atipci_be->backend.mem_type = DRM_BO_MEM_TT;
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atipci_be->gart_info = info;
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atipci_be->gart_flush_fn = gart_flush_fn;
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atipci_be->dev = dev;
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return &atipci_be->backend;
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}
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@ -846,10 +846,13 @@ typedef struct drm_agp_ttm_backend {
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typedef struct ati_pcigart_ttm_backend {
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drm_ttm_backend_t backend;
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int populated;
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void (*gart_flush_fn)(struct drm_device *dev);
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struct ati_pcigart_info *gart_info;
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unsigned long offset;
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struct page **pages;
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int num_pages;
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int bound;
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drm_device_t *dev;
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} ati_pcigart_ttm_backend_t;
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static __inline__ int drm_core_check_feature(struct drm_device *dev,
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@ -33,7 +33,6 @@
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#include "radeon_drm.h"
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#include "radeon_drv.h"
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drm_ttm_backend_t *radeon_create_ttm_backend_entry(drm_device_t * dev)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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@ -41,7 +40,7 @@ drm_ttm_backend_t *radeon_create_ttm_backend_entry(drm_device_t * dev)
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if(dev_priv->flags & RADEON_IS_AGP)
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return drm_agp_init_ttm(dev);
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else
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return ati_pcigart_init_ttm(dev, &dev_priv->gart_info);
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return ati_pcigart_init_ttm(dev, &dev_priv->gart_info, radeon_gart_flush);
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}
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int radeon_fence_types(drm_buffer_object_t *bo, uint32_t * class, uint32_t * type)
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@ -1384,6 +1384,26 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
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}
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}
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void radeon_gart_flush(struct drm_device *dev)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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if (dev_priv->flags & RADEON_IS_IGPGART) {
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RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
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RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
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RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
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RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
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} else if (dev_priv->flags & RADEON_IS_PCIE) {
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} else {
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}
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}
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static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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@ -344,6 +344,7 @@ extern int radeon_cp_resume(DRM_IOCTL_ARGS);
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extern int radeon_engine_reset(DRM_IOCTL_ARGS);
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extern int radeon_fullscreen(DRM_IOCTL_ARGS);
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extern int radeon_cp_buffers(DRM_IOCTL_ARGS);
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extern void radeon_gart_flush(struct drm_device *dev);
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extern void radeon_freelist_reset(drm_device_t * dev);
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extern drm_buf_t *radeon_freelist_get(drm_device_t * dev);
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