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dos2unix and Lindent

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Ian Romanick 2007-06-26 13:10:30 -07:00
parent 7af9d67037
commit 434657a258
13 changed files with 5765 additions and 5913 deletions
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705
linux-core/xgi_cmdlist.c
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@ -1,348 +1,357 @@
/****************************************************************************
* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
* *
* All Rights Reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
* *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
***************************************************************************/
#include "xgi_types.h"
#include "xgi_linux.h"
#include "xgi_drv.h"
#include "xgi_regs.h"
#include "xgi_misc.h"
#include "xgi_cmdlist.h"
U32 s_emptyBegin[AGPCMDLIST_BEGIN_SIZE] =
{
0x10000000, // 3D Type Begin, Invalid
0x80000004, // Length = 4;
0x00000000,
0x00000000
};
U32 s_flush2D[AGPCMDLIST_FLUSH_CMD_LEN] =
{
FLUSH_2D,
FLUSH_2D,
FLUSH_2D,
FLUSH_2D
};
xgi_cmdring_info_t s_cmdring;
static void addFlush2D(xgi_info_t *info);
static U32 getCurBatchBeginPort(xgi_cmd_info_t *pCmdInfo);
static void triggerHWCommandList(xgi_info_t *info, U32 triggerCounter);
static void xgi_cmdlist_reset(void);
int xgi_cmdlist_initialize(xgi_info_t *info, U32 size)
{
//xgi_mem_req_t mem_req;
xgi_mem_alloc_t mem_alloc;
//mem_req.size = size;
xgi_pcie_alloc(info, size, PCIE_2D, &mem_alloc);
if ((mem_alloc.size == 0) && (mem_alloc.hw_addr == 0))
{
return -1;
}
s_cmdring._cmdRingSize = mem_alloc.size;
s_cmdring._cmdRingBuffer = mem_alloc.hw_addr;
s_cmdring._cmdRingBusAddr = mem_alloc.bus_addr;
s_cmdring._lastBatchStartAddr = 0;
s_cmdring._cmdRingOffset = 0;
return 1;
}
void xgi_submit_cmdlist(xgi_info_t *info, xgi_cmd_info_t *pCmdInfo)
{
U32 beginPort;
/** XGI_INFO("Jong-xgi_submit_cmdlist-Begin \n"); **/
/* Jong 05/25/2006 */
/* return; */
beginPort = getCurBatchBeginPort(pCmdInfo);
XGI_INFO("Jong-xgi_submit_cmdlist-After getCurBatchBeginPort() \n");
/* Jong 05/25/2006 */
/* return; */
if (s_cmdring._lastBatchStartAddr == 0)
{
U32 portOffset;
/* Jong 06/13/2006; remove marked for system hang test */
/* xgi_waitfor_pci_idle(info); */
/* Jong 06132006; BASE_3D_ENG=0x2800 */
/* beginPort: 2D: 0x30 */
portOffset = BASE_3D_ENG + beginPort;
// Enable PCI Trigger Mode
XGI_INFO("Jong-xgi_submit_cmdlist-Enable PCI Trigger Mode \n");
/* Jong 05/25/2006 */
/* return; */
/* Jong 06/13/2006; M2REG_AUTO_LINK_SETTING_ADDRESS=0x10 */
XGI_INFO("Jong-M2REG_AUTO_LINK_SETTING_ADDRESS=0x%lx \n", M2REG_AUTO_LINK_SETTING_ADDRESS);
XGI_INFO("Jong-M2REG_CLEAR_COUNTERS_MASK=0x%lx \n", M2REG_CLEAR_COUNTERS_MASK);
XGI_INFO("Jong-(M2REG_AUTO_LINK_SETTING_ADDRESS << 22)=0x%lx \n", (M2REG_AUTO_LINK_SETTING_ADDRESS << 22));
XGI_INFO("Jong-M2REG_PCI_TRIGGER_MODE_MASK=0x%lx \n\n", M2REG_PCI_TRIGGER_MODE_MASK);
/* Jong 06/14/2006; 0x400001a */
XGI_INFO("Jong-(M2REG_AUTO_LINK_SETTING_ADDRESS << 22)|M2REG_CLEAR_COUNTERS_MASK|0x08|M2REG_PCI_TRIGGER_MODE_MASK=0x%lx \n",
(M2REG_AUTO_LINK_SETTING_ADDRESS << 22)|M2REG_CLEAR_COUNTERS_MASK|0x08|M2REG_PCI_TRIGGER_MODE_MASK);
dwWriteReg(BASE_3D_ENG + M2REG_AUTO_LINK_SETTING_ADDRESS,
(M2REG_AUTO_LINK_SETTING_ADDRESS << 22) |
M2REG_CLEAR_COUNTERS_MASK |
0x08 |
M2REG_PCI_TRIGGER_MODE_MASK);
/* Jong 05/25/2006 */
XGI_INFO("Jong-xgi_submit_cmdlist-After dwWriteReg() \n");
/* return; */ /* OK */
/* Jong 06/14/2006; 0x400000a */
XGI_INFO("Jong-(M2REG_AUTO_LINK_SETTING_ADDRESS << 22)|0x08|M2REG_PCI_TRIGGER_MODE_MASK=0x%lx \n",
(M2REG_AUTO_LINK_SETTING_ADDRESS << 22)|0x08|M2REG_PCI_TRIGGER_MODE_MASK);
dwWriteReg(BASE_3D_ENG + M2REG_AUTO_LINK_SETTING_ADDRESS,
(M2REG_AUTO_LINK_SETTING_ADDRESS << 22) |
0x08 |
M2REG_PCI_TRIGGER_MODE_MASK);
// Send PCI begin command
XGI_INFO("Jong-xgi_submit_cmdlist-Send PCI begin command \n");
/* return; */
XGI_INFO("Jong-xgi_submit_cmdlist-portOffset=%d \n", portOffset);
XGI_INFO("Jong-xgi_submit_cmdlist-beginPort=%d \n", beginPort);
/* beginPort = 48; */
/* 0xc100000 */
dwWriteReg(portOffset, (beginPort<<22) + (BEGIN_VALID_MASK) + pCmdInfo->_curDebugID);
XGI_INFO("Jong-(beginPort<<22)=0x%lx \n", (beginPort<<22));
XGI_INFO("Jong-(BEGIN_VALID_MASK)=0x%lx \n", BEGIN_VALID_MASK);
XGI_INFO("Jong- pCmdInfo->_curDebugID=0x%lx \n", pCmdInfo->_curDebugID);
XGI_INFO("Jong- (beginPort<<22) + (BEGIN_VALID_MASK) + pCmdInfo->_curDebugID=0x%lx \n", (beginPort<<22) + (BEGIN_VALID_MASK) + pCmdInfo->_curDebugID);
XGI_INFO("Jong-xgi_submit_cmdlist-Send PCI begin command- After \n");
/* return; */ /* OK */
/* 0x80000024 */
dwWriteReg(portOffset+4, BEGIN_LINK_ENABLE_MASK + pCmdInfo->_firstSize);
XGI_INFO("Jong- BEGIN_LINK_ENABLE_MASK=0x%lx \n", BEGIN_LINK_ENABLE_MASK);
XGI_INFO("Jong- pCmdInfo->_firstSize=0x%lx \n", pCmdInfo->_firstSize);
XGI_INFO("Jong- BEGIN_LINK_ENABLE_MASK + pCmdInfo->_firstSize=0x%lx \n", BEGIN_LINK_ENABLE_MASK + pCmdInfo->_firstSize);
XGI_INFO("Jong-xgi_submit_cmdlist-dwWriteReg-1 \n");
/* 0x1010000 */
dwWriteReg(portOffset+8, (pCmdInfo->_firstBeginAddr >> 4));
XGI_INFO("Jong- pCmdInfo->_firstBeginAddr=0x%lx \n", pCmdInfo->_firstBeginAddr);
XGI_INFO("Jong- (pCmdInfo->_firstBeginAddr >> 4)=0x%lx \n", (pCmdInfo->_firstBeginAddr >> 4));
XGI_INFO("Jong-xgi_submit_cmdlist-dwWriteReg-2 \n");
/* Jong 06/13/2006 */
xgi_dump_register(info);
/* Jong 06/12/2006; system hang; marked for test */
dwWriteReg(portOffset+12, 0);
XGI_INFO("Jong-xgi_submit_cmdlist-dwWriteReg-3 \n");
/* Jong 06/13/2006; remove marked for system hang test */
/* xgi_waitfor_pci_idle(info); */
}
else
{
XGI_INFO("Jong-xgi_submit_cmdlist-s_cmdring._lastBatchStartAddr != 0 \n");
U32 *lastBatchVirtAddr;
/* Jong 05/25/2006 */
/* return; */
if (pCmdInfo->_firstBeginType == BTYPE_3D)
{
addFlush2D(info);
}
lastBatchVirtAddr = (U32*) xgi_find_pcie_virt(info, s_cmdring._lastBatchStartAddr);
lastBatchVirtAddr[1] = BEGIN_LINK_ENABLE_MASK + pCmdInfo->_firstSize;
lastBatchVirtAddr[2] = pCmdInfo->_firstBeginAddr >> 4;
lastBatchVirtAddr[3] = 0;
//barrier();
lastBatchVirtAddr[0] = (beginPort<<22) + (BEGIN_VALID_MASK) + (0xffff & pCmdInfo->_curDebugID);
/* Jong 06/12/2006; system hang; marked for test */
triggerHWCommandList(info, pCmdInfo->_beginCount);
XGI_INFO("Jong-xgi_submit_cmdlist-s_cmdring._lastBatchStartAddr != 0 - End\n");
}
s_cmdring._lastBatchStartAddr = pCmdInfo->_lastBeginAddr;
XGI_INFO("Jong-xgi_submit_cmdlist-End \n");
}
/*
state: 0 - console
1 - graphic
2 - fb
3 - logout
*/
void xgi_state_change(xgi_info_t *info, xgi_state_info_t *pStateInfo)
{
#define STATE_CONSOLE 0
#define STATE_GRAPHIC 1
#define STATE_FBTERM 2
#define STATE_LOGOUT 3
#define STATE_REBOOT 4
#define STATE_SHUTDOWN 5
if ((pStateInfo->_fromState == STATE_GRAPHIC)
&& (pStateInfo->_toState == STATE_CONSOLE))
{
XGI_INFO("[kd] I see, now is to leaveVT\n");
// stop to received batch
}
else if ((pStateInfo->_fromState == STATE_CONSOLE)
&& (pStateInfo->_toState == STATE_GRAPHIC))
{
XGI_INFO("[kd] I see, now is to enterVT\n");
xgi_cmdlist_reset();
}
else if ((pStateInfo->_fromState == STATE_GRAPHIC)
&& ( (pStateInfo->_toState == STATE_LOGOUT)
||(pStateInfo->_toState == STATE_REBOOT)
||(pStateInfo->_toState == STATE_SHUTDOWN)))
{
XGI_INFO("[kd] I see, not is to exit from X\n");
// stop to received batch
}
else
{
XGI_ERROR("[kd] Should not happen\n");
}
}
void xgi_cmdlist_reset(void)
{
s_cmdring._lastBatchStartAddr = 0;
s_cmdring._cmdRingOffset = 0;
}
void xgi_cmdlist_cleanup(xgi_info_t *info)
{
if (s_cmdring._cmdRingBuffer != 0)
{
xgi_pcie_free(info, s_cmdring._cmdRingBusAddr);
s_cmdring._cmdRingBuffer = 0;
s_cmdring._cmdRingOffset = 0;
s_cmdring._cmdRingSize = 0;
}
}
static void triggerHWCommandList(xgi_info_t *info, U32 triggerCounter)
{
static U32 s_triggerID = 1;
//Fix me, currently we just trigger one time
while (triggerCounter--)
{
dwWriteReg(BASE_3D_ENG + M2REG_PCI_TRIGGER_REGISTER_ADDRESS,
0x05000000 + (0xffff & s_triggerID++));
// xgi_waitfor_pci_idle(info);
}
}
static U32 getCurBatchBeginPort(xgi_cmd_info_t *pCmdInfo)
{
// Convert the batch type to begin port ID
switch(pCmdInfo->_firstBeginType)
{
case BTYPE_2D:
return 0x30;
case BTYPE_3D:
return 0x40;
case BTYPE_FLIP:
return 0x50;
case BTYPE_CTRL:
return 0x20;
default:
//ASSERT(0);
return 0xff;
}
}
static void addFlush2D(xgi_info_t *info)
{
U32 *flushBatchVirtAddr;
U32 flushBatchHWAddr;
U32 *lastBatchVirtAddr;
/* check buf is large enough to contain a new flush batch */
if ((s_cmdring._cmdRingOffset + 0x20) >= s_cmdring._cmdRingSize)
{
s_cmdring._cmdRingOffset = 0;
}
flushBatchHWAddr = s_cmdring._cmdRingBuffer + s_cmdring._cmdRingOffset;
flushBatchVirtAddr = (U32*) xgi_find_pcie_virt(info, flushBatchHWAddr);
/* not using memcpy for I assume the address is discrete */
*(flushBatchVirtAddr + 0) = 0x10000000;
*(flushBatchVirtAddr + 1) = 0x80000004; /* size = 0x04 dwords */
*(flushBatchVirtAddr + 2) = 0x00000000;
*(flushBatchVirtAddr + 3) = 0x00000000;
*(flushBatchVirtAddr + 4) = FLUSH_2D;
*(flushBatchVirtAddr + 5) = FLUSH_2D;
*(flushBatchVirtAddr + 6) = FLUSH_2D;
*(flushBatchVirtAddr + 7) = FLUSH_2D;
// ASSERT(s_cmdring._lastBatchStartAddr != NULL);
lastBatchVirtAddr = (U32*) xgi_find_pcie_virt(info, s_cmdring._lastBatchStartAddr);
lastBatchVirtAddr[1] = BEGIN_LINK_ENABLE_MASK + 0x08;
lastBatchVirtAddr[2] = flushBatchHWAddr >> 4;
lastBatchVirtAddr[3] = 0;
//barrier();
// BTYPE_CTRL & NO debugID
lastBatchVirtAddr[0] = (0x20<<22) + (BEGIN_VALID_MASK);
triggerHWCommandList(info, 1);
s_cmdring._cmdRingOffset += 0x20;
s_cmdring._lastBatchStartAddr = flushBatchHWAddr;
}
/****************************************************************************
* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
* *
* All Rights Reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
* *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
***************************************************************************/
#include "xgi_types.h"
#include "xgi_linux.h"
#include "xgi_drv.h"
#include "xgi_regs.h"
#include "xgi_misc.h"
#include "xgi_cmdlist.h"
U32 s_emptyBegin[AGPCMDLIST_BEGIN_SIZE] = {
0x10000000, // 3D Type Begin, Invalid
0x80000004, // Length = 4;
0x00000000,
0x00000000
};
U32 s_flush2D[AGPCMDLIST_FLUSH_CMD_LEN] = {
FLUSH_2D,
FLUSH_2D,
FLUSH_2D,
FLUSH_2D
};
xgi_cmdring_info_t s_cmdring;
static void addFlush2D(xgi_info_t * info);
static U32 getCurBatchBeginPort(xgi_cmd_info_t * pCmdInfo);
static void triggerHWCommandList(xgi_info_t * info, U32 triggerCounter);
static void xgi_cmdlist_reset(void);
int xgi_cmdlist_initialize(xgi_info_t * info, U32 size)
{
//xgi_mem_req_t mem_req;
xgi_mem_alloc_t mem_alloc;
//mem_req.size = size;
xgi_pcie_alloc(info, size, PCIE_2D, &mem_alloc);
if ((mem_alloc.size == 0) && (mem_alloc.hw_addr == 0)) {
return -1;
}
s_cmdring._cmdRingSize = mem_alloc.size;
s_cmdring._cmdRingBuffer = mem_alloc.hw_addr;
s_cmdring._cmdRingBusAddr = mem_alloc.bus_addr;
s_cmdring._lastBatchStartAddr = 0;
s_cmdring._cmdRingOffset = 0;
return 1;
}
void xgi_submit_cmdlist(xgi_info_t * info, xgi_cmd_info_t * pCmdInfo)
{
U32 beginPort;
/** XGI_INFO("Jong-xgi_submit_cmdlist-Begin \n"); **/
/* Jong 05/25/2006 */
/* return; */
beginPort = getCurBatchBeginPort(pCmdInfo);
XGI_INFO("Jong-xgi_submit_cmdlist-After getCurBatchBeginPort() \n");
/* Jong 05/25/2006 */
/* return; */
if (s_cmdring._lastBatchStartAddr == 0) {
U32 portOffset;
/* Jong 06/13/2006; remove marked for system hang test */
/* xgi_waitfor_pci_idle(info); */
/* Jong 06132006; BASE_3D_ENG=0x2800 */
/* beginPort: 2D: 0x30 */
portOffset = BASE_3D_ENG + beginPort;
// Enable PCI Trigger Mode
XGI_INFO("Jong-xgi_submit_cmdlist-Enable PCI Trigger Mode \n");
/* Jong 05/25/2006 */
/* return; */
/* Jong 06/13/2006; M2REG_AUTO_LINK_SETTING_ADDRESS=0x10 */
XGI_INFO("Jong-M2REG_AUTO_LINK_SETTING_ADDRESS=0x%lx \n",
M2REG_AUTO_LINK_SETTING_ADDRESS);
XGI_INFO("Jong-M2REG_CLEAR_COUNTERS_MASK=0x%lx \n",
M2REG_CLEAR_COUNTERS_MASK);
XGI_INFO
("Jong-(M2REG_AUTO_LINK_SETTING_ADDRESS << 22)=0x%lx \n",
(M2REG_AUTO_LINK_SETTING_ADDRESS << 22));
XGI_INFO("Jong-M2REG_PCI_TRIGGER_MODE_MASK=0x%lx \n\n",
M2REG_PCI_TRIGGER_MODE_MASK);
/* Jong 06/14/2006; 0x400001a */
XGI_INFO
("Jong-(M2REG_AUTO_LINK_SETTING_ADDRESS << 22)|M2REG_CLEAR_COUNTERS_MASK|0x08|M2REG_PCI_TRIGGER_MODE_MASK=0x%lx \n",
(M2REG_AUTO_LINK_SETTING_ADDRESS << 22) |
M2REG_CLEAR_COUNTERS_MASK | 0x08 |
M2REG_PCI_TRIGGER_MODE_MASK);
dwWriteReg(BASE_3D_ENG + M2REG_AUTO_LINK_SETTING_ADDRESS,
(M2REG_AUTO_LINK_SETTING_ADDRESS << 22) |
M2REG_CLEAR_COUNTERS_MASK | 0x08 |
M2REG_PCI_TRIGGER_MODE_MASK);
/* Jong 05/25/2006 */
XGI_INFO("Jong-xgi_submit_cmdlist-After dwWriteReg() \n");
/* return; *//* OK */
/* Jong 06/14/2006; 0x400000a */
XGI_INFO
("Jong-(M2REG_AUTO_LINK_SETTING_ADDRESS << 22)|0x08|M2REG_PCI_TRIGGER_MODE_MASK=0x%lx \n",
(M2REG_AUTO_LINK_SETTING_ADDRESS << 22) | 0x08 |
M2REG_PCI_TRIGGER_MODE_MASK);
dwWriteReg(BASE_3D_ENG + M2REG_AUTO_LINK_SETTING_ADDRESS,
(M2REG_AUTO_LINK_SETTING_ADDRESS << 22) | 0x08 |
M2REG_PCI_TRIGGER_MODE_MASK);
// Send PCI begin command
XGI_INFO("Jong-xgi_submit_cmdlist-Send PCI begin command \n");
/* return; */
XGI_INFO("Jong-xgi_submit_cmdlist-portOffset=%d \n",
portOffset);
XGI_INFO("Jong-xgi_submit_cmdlist-beginPort=%d \n", beginPort);
/* beginPort = 48; */
/* 0xc100000 */
dwWriteReg(portOffset,
(beginPort << 22) + (BEGIN_VALID_MASK) +
pCmdInfo->_curDebugID);
XGI_INFO("Jong-(beginPort<<22)=0x%lx \n", (beginPort << 22));
XGI_INFO("Jong-(BEGIN_VALID_MASK)=0x%lx \n", BEGIN_VALID_MASK);
XGI_INFO("Jong- pCmdInfo->_curDebugID=0x%lx \n",
pCmdInfo->_curDebugID);
XGI_INFO
("Jong- (beginPort<<22) + (BEGIN_VALID_MASK) + pCmdInfo->_curDebugID=0x%lx \n",
(beginPort << 22) + (BEGIN_VALID_MASK) +
pCmdInfo->_curDebugID);
XGI_INFO
("Jong-xgi_submit_cmdlist-Send PCI begin command- After \n");
/* return; *//* OK */
/* 0x80000024 */
dwWriteReg(portOffset + 4,
BEGIN_LINK_ENABLE_MASK + pCmdInfo->_firstSize);
XGI_INFO("Jong- BEGIN_LINK_ENABLE_MASK=0x%lx \n",
BEGIN_LINK_ENABLE_MASK);
XGI_INFO("Jong- pCmdInfo->_firstSize=0x%lx \n",
pCmdInfo->_firstSize);
XGI_INFO
("Jong- BEGIN_LINK_ENABLE_MASK + pCmdInfo->_firstSize=0x%lx \n",
BEGIN_LINK_ENABLE_MASK + pCmdInfo->_firstSize);
XGI_INFO("Jong-xgi_submit_cmdlist-dwWriteReg-1 \n");
/* 0x1010000 */
dwWriteReg(portOffset + 8, (pCmdInfo->_firstBeginAddr >> 4));
XGI_INFO("Jong- pCmdInfo->_firstBeginAddr=0x%lx \n",
pCmdInfo->_firstBeginAddr);
XGI_INFO("Jong- (pCmdInfo->_firstBeginAddr >> 4)=0x%lx \n",
(pCmdInfo->_firstBeginAddr >> 4));
XGI_INFO("Jong-xgi_submit_cmdlist-dwWriteReg-2 \n");
/* Jong 06/13/2006 */
xgi_dump_register(info);
/* Jong 06/12/2006; system hang; marked for test */
dwWriteReg(portOffset + 12, 0);
XGI_INFO("Jong-xgi_submit_cmdlist-dwWriteReg-3 \n");
/* Jong 06/13/2006; remove marked for system hang test */
/* xgi_waitfor_pci_idle(info); */
} else {
XGI_INFO
("Jong-xgi_submit_cmdlist-s_cmdring._lastBatchStartAddr != 0 \n");
U32 *lastBatchVirtAddr;
/* Jong 05/25/2006 */
/* return; */
if (pCmdInfo->_firstBeginType == BTYPE_3D) {
addFlush2D(info);
}
lastBatchVirtAddr =
(U32 *) xgi_find_pcie_virt(info,
s_cmdring._lastBatchStartAddr);
lastBatchVirtAddr[1] =
BEGIN_LINK_ENABLE_MASK + pCmdInfo->_firstSize;
lastBatchVirtAddr[2] = pCmdInfo->_firstBeginAddr >> 4;
lastBatchVirtAddr[3] = 0;
//barrier();
lastBatchVirtAddr[0] =
(beginPort << 22) + (BEGIN_VALID_MASK) +
(0xffff & pCmdInfo->_curDebugID);
/* Jong 06/12/2006; system hang; marked for test */
triggerHWCommandList(info, pCmdInfo->_beginCount);
XGI_INFO
("Jong-xgi_submit_cmdlist-s_cmdring._lastBatchStartAddr != 0 - End\n");
}
s_cmdring._lastBatchStartAddr = pCmdInfo->_lastBeginAddr;
XGI_INFO("Jong-xgi_submit_cmdlist-End \n");
}
/*
state: 0 - console
1 - graphic
2 - fb
3 - logout
*/
void xgi_state_change(xgi_info_t * info, xgi_state_info_t * pStateInfo)
{
#define STATE_CONSOLE 0
#define STATE_GRAPHIC 1
#define STATE_FBTERM 2
#define STATE_LOGOUT 3
#define STATE_REBOOT 4
#define STATE_SHUTDOWN 5
if ((pStateInfo->_fromState == STATE_GRAPHIC)
&& (pStateInfo->_toState == STATE_CONSOLE)) {
XGI_INFO("[kd] I see, now is to leaveVT\n");
// stop to received batch
} else if ((pStateInfo->_fromState == STATE_CONSOLE)
&& (pStateInfo->_toState == STATE_GRAPHIC)) {
XGI_INFO("[kd] I see, now is to enterVT\n");
xgi_cmdlist_reset();
} else if ((pStateInfo->_fromState == STATE_GRAPHIC)
&& ((pStateInfo->_toState == STATE_LOGOUT)
|| (pStateInfo->_toState == STATE_REBOOT)
|| (pStateInfo->_toState == STATE_SHUTDOWN))) {
XGI_INFO("[kd] I see, not is to exit from X\n");
// stop to received batch
} else {
XGI_ERROR("[kd] Should not happen\n");
}
}
void xgi_cmdlist_reset(void)
{
s_cmdring._lastBatchStartAddr = 0;
s_cmdring._cmdRingOffset = 0;
}
void xgi_cmdlist_cleanup(xgi_info_t * info)
{
if (s_cmdring._cmdRingBuffer != 0) {
xgi_pcie_free(info, s_cmdring._cmdRingBusAddr);
s_cmdring._cmdRingBuffer = 0;
s_cmdring._cmdRingOffset = 0;
s_cmdring._cmdRingSize = 0;
}
}
static void triggerHWCommandList(xgi_info_t * info, U32 triggerCounter)
{
static U32 s_triggerID = 1;
//Fix me, currently we just trigger one time
while (triggerCounter--) {
dwWriteReg(BASE_3D_ENG + M2REG_PCI_TRIGGER_REGISTER_ADDRESS,
0x05000000 + (0xffff & s_triggerID++));
// xgi_waitfor_pci_idle(info);
}
}
static U32 getCurBatchBeginPort(xgi_cmd_info_t * pCmdInfo)
{
// Convert the batch type to begin port ID
switch (pCmdInfo->_firstBeginType) {
case BTYPE_2D:
return 0x30;
case BTYPE_3D:
return 0x40;
case BTYPE_FLIP:
return 0x50;
case BTYPE_CTRL:
return 0x20;
default:
//ASSERT(0);
return 0xff;
}
}
static void addFlush2D(xgi_info_t * info)
{
U32 *flushBatchVirtAddr;
U32 flushBatchHWAddr;
U32 *lastBatchVirtAddr;
/* check buf is large enough to contain a new flush batch */
if ((s_cmdring._cmdRingOffset + 0x20) >= s_cmdring._cmdRingSize) {
s_cmdring._cmdRingOffset = 0;
}
flushBatchHWAddr = s_cmdring._cmdRingBuffer + s_cmdring._cmdRingOffset;
flushBatchVirtAddr = (U32 *) xgi_find_pcie_virt(info, flushBatchHWAddr);
/* not using memcpy for I assume the address is discrete */
*(flushBatchVirtAddr + 0) = 0x10000000;
*(flushBatchVirtAddr + 1) = 0x80000004; /* size = 0x04 dwords */
*(flushBatchVirtAddr + 2) = 0x00000000;
*(flushBatchVirtAddr + 3) = 0x00000000;
*(flushBatchVirtAddr + 4) = FLUSH_2D;
*(flushBatchVirtAddr + 5) = FLUSH_2D;
*(flushBatchVirtAddr + 6) = FLUSH_2D;
*(flushBatchVirtAddr + 7) = FLUSH_2D;
// ASSERT(s_cmdring._lastBatchStartAddr != NULL);
lastBatchVirtAddr =
(U32 *) xgi_find_pcie_virt(info, s_cmdring._lastBatchStartAddr);
lastBatchVirtAddr[1] = BEGIN_LINK_ENABLE_MASK + 0x08;
lastBatchVirtAddr[2] = flushBatchHWAddr >> 4;
lastBatchVirtAddr[3] = 0;
//barrier();
// BTYPE_CTRL & NO debugID
lastBatchVirtAddr[0] = (0x20 << 22) + (BEGIN_VALID_MASK);
triggerHWCommandList(info, 1);
s_cmdring._cmdRingOffset += 0x20;
s_cmdring._lastBatchStartAddr = flushBatchHWAddr;
}

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linux-core/xgi_cmdlist.h
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@ -1,79 +1,76 @@
/****************************************************************************
* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
* *
* All Rights Reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
* *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
***************************************************************************/
#ifndef _XGI_CMDLIST_H_
#define _XGI_CMDLIST_H_
#define ONE_BIT_MASK 0x1
#define TWENTY_BIT_MASK 0xfffff
#define M2REG_FLUSH_2D_ENGINE_MASK (ONE_BIT_MASK<<20)
#define M2REG_FLUSH_3D_ENGINE_MASK TWENTY_BIT_MASK
#define M2REG_FLUSH_FLIP_ENGINE_MASK (ONE_BIT_MASK<<21)
#define BASE_3D_ENG 0x2800
#define M2REG_AUTO_LINK_SETTING_ADDRESS 0x10
#define M2REG_CLEAR_COUNTERS_MASK (ONE_BIT_MASK<<4)
#define M2REG_PCI_TRIGGER_MODE_MASK (ONE_BIT_MASK<<1)
#define BEGIN_VALID_MASK (ONE_BIT_MASK<<20)
#define BEGIN_LINK_ENABLE_MASK (ONE_BIT_MASK<<31)
#define M2REG_PCI_TRIGGER_REGISTER_ADDRESS 0x14
typedef enum
{
FLUSH_2D = M2REG_FLUSH_2D_ENGINE_MASK,
FLUSH_3D = M2REG_FLUSH_3D_ENGINE_MASK,
FLUSH_FLIP = M2REG_FLUSH_FLIP_ENGINE_MASK
}FLUSH_CODE;
typedef enum
{
AGPCMDLIST_SCRATCH_SIZE = 0x100,
AGPCMDLIST_BEGIN_SIZE = 0x004,
AGPCMDLIST_3D_SCRATCH_CMD_SIZE = 0x004,
AGPCMDLIST_2D_SCRATCH_CMD_SIZE = 0x00c,
AGPCMDLIST_FLUSH_CMD_LEN = 0x004,
AGPCMDLIST_DUMY_END_BATCH_LEN = AGPCMDLIST_BEGIN_SIZE
}CMD_SIZE;
typedef struct xgi_cmdring_info_s
{
U32 _cmdRingSize;
U32 _cmdRingBuffer;
U32 _cmdRingBusAddr;
U32 _lastBatchStartAddr;
U32 _cmdRingOffset;
}xgi_cmdring_info_t;
extern int xgi_cmdlist_initialize(xgi_info_t *info, U32 size);
extern void xgi_submit_cmdlist(xgi_info_t *info, xgi_cmd_info_t * pCmdInfo);
extern void xgi_state_change(xgi_info_t *info, xgi_state_info_t * pStateInfo);
extern void xgi_cmdlist_cleanup(xgi_info_t *info);
#endif /* _XGI_CMDLIST_H_ */
/****************************************************************************
* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
* *
* All Rights Reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
* *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
***************************************************************************/
#ifndef _XGI_CMDLIST_H_
#define _XGI_CMDLIST_H_
#define ONE_BIT_MASK 0x1
#define TWENTY_BIT_MASK 0xfffff
#define M2REG_FLUSH_2D_ENGINE_MASK (ONE_BIT_MASK<<20)
#define M2REG_FLUSH_3D_ENGINE_MASK TWENTY_BIT_MASK
#define M2REG_FLUSH_FLIP_ENGINE_MASK (ONE_BIT_MASK<<21)
#define BASE_3D_ENG 0x2800
#define M2REG_AUTO_LINK_SETTING_ADDRESS 0x10
#define M2REG_CLEAR_COUNTERS_MASK (ONE_BIT_MASK<<4)
#define M2REG_PCI_TRIGGER_MODE_MASK (ONE_BIT_MASK<<1)
#define BEGIN_VALID_MASK (ONE_BIT_MASK<<20)
#define BEGIN_LINK_ENABLE_MASK (ONE_BIT_MASK<<31)
#define M2REG_PCI_TRIGGER_REGISTER_ADDRESS 0x14
typedef enum {
FLUSH_2D = M2REG_FLUSH_2D_ENGINE_MASK,
FLUSH_3D = M2REG_FLUSH_3D_ENGINE_MASK,
FLUSH_FLIP = M2REG_FLUSH_FLIP_ENGINE_MASK
} FLUSH_CODE;
typedef enum {
AGPCMDLIST_SCRATCH_SIZE = 0x100,
AGPCMDLIST_BEGIN_SIZE = 0x004,
AGPCMDLIST_3D_SCRATCH_CMD_SIZE = 0x004,
AGPCMDLIST_2D_SCRATCH_CMD_SIZE = 0x00c,
AGPCMDLIST_FLUSH_CMD_LEN = 0x004,
AGPCMDLIST_DUMY_END_BATCH_LEN = AGPCMDLIST_BEGIN_SIZE
} CMD_SIZE;
typedef struct xgi_cmdring_info_s {
U32 _cmdRingSize;
U32 _cmdRingBuffer;
U32 _cmdRingBusAddr;
U32 _lastBatchStartAddr;
U32 _cmdRingOffset;
} xgi_cmdring_info_t;
extern int xgi_cmdlist_initialize(xgi_info_t * info, U32 size);
extern void xgi_submit_cmdlist(xgi_info_t * info, xgi_cmd_info_t * pCmdInfo);
extern void xgi_state_change(xgi_info_t * info, xgi_state_info_t * pStateInfo);
extern void xgi_cmdlist_cleanup(xgi_info_t * info);
#endif /* _XGI_CMDLIST_H_ */

3174
linux-core/xgi_drv.c
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728
linux-core/xgi_drv.h
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@ -1,364 +1,364 @@
/****************************************************************************
* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
* *
* All Rights Reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
* *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
***************************************************************************/
#ifndef _XGI_DRV_H_
#define _XGI_DRV_H_
#define XGI_MAJOR_VERSION 0
#define XGI_MINOR_VERSION 7
#define XGI_PATCHLEVEL 5
#define XGI_DRV_VERSION "0.7.5"
#ifndef XGI_DRV_NAME
#define XGI_DRV_NAME "xgi"
#endif
/*
* xgi reserved major device number, Set this to 0 to
* request dynamic major number allocation.
*/
#ifndef XGI_DEV_MAJOR
#define XGI_DEV_MAJOR 0
#endif
#ifndef XGI_MAX_DEVICES
#define XGI_MAX_DEVICES 1
#endif
/* Jong 06/06/2006 */
/* #define XGI_DEBUG */
#ifndef PCI_VENDOR_ID_XGI
/*
#define PCI_VENDOR_ID_XGI 0x1023
*/
#define PCI_VENDOR_ID_XGI 0x18CA
#endif
#ifndef PCI_DEVICE_ID_XP5
#define PCI_DEVICE_ID_XP5 0x2200
#endif
#ifndef PCI_DEVICE_ID_XG47
#define PCI_DEVICE_ID_XG47 0x0047
#endif
/* Macros to make printk easier */
#define XGI_ERROR(fmt, arg...) \
printk(KERN_ERR "[" XGI_DRV_NAME ":%s] *ERROR* " fmt, __FUNCTION__, ##arg)
#define XGI_MEM_ERROR(area, fmt, arg...) \
printk(KERN_ERR "[" XGI_DRV_NAME ":%s] *ERROR* " fmt, __FUNCTION__, ##arg)
/* #define XGI_DEBUG */
#ifdef XGI_DEBUG
#define XGI_INFO(fmt, arg...) \
printk(KERN_ALERT "[" XGI_DRV_NAME ":%s] " fmt, __FUNCTION__, ##arg)
/* printk(KERN_INFO "[" XGI_DRV_NAME ":%s] " fmt, __FUNCTION__, ##arg) */
#else
#define XGI_INFO(fmt, arg...) do { } while (0)
#endif
/* device name length; must be atleast 8 */
#define XGI_DEVICE_NAME_LENGTH 40
/* need a fake device number for control device; just to flag it for msgs */
#define XGI_CONTROL_DEVICE_NUMBER 100
typedef struct {
U32 base; // pcie base is different from fb base
U32 size;
U8 *vbase;
} xgi_aperture_t;
typedef struct xgi_screen_info_s {
U32 scrn_start;
U32 scrn_xres;
U32 scrn_yres;
U32 scrn_bpp;
U32 scrn_pitch;
} xgi_screen_info_t;
typedef struct xgi_sarea_info_s {
U32 bus_addr;
U32 size;
} xgi_sarea_info_t;
typedef struct xgi_info_s {
struct pci_dev *dev;
int flags;
int device_number;
int bus; /* PCI config info */
int slot;
int vendor_id;
U32 device_id;
U8 revision_id;
/* physical characteristics */
xgi_aperture_t mmio;
xgi_aperture_t fb;
xgi_aperture_t pcie;
xgi_screen_info_t scrn_info;
xgi_sarea_info_t sarea_info;
/* look up table parameters */
U32 *lut_base;
U32 lutPageSize;
U32 lutPageOrder;
U32 isLUTInLFB;
U32 sdfbPageSize;
U32 pcie_config;
U32 pcie_status;
U32 irq;
atomic_t use_count;
/* keep track of any pending bottom halfes */
struct tasklet_struct tasklet;
spinlock_t info_lock;
struct semaphore info_sem;
struct semaphore fb_sem;
struct semaphore pcie_sem;
} xgi_info_t;
typedef struct xgi_ioctl_post_vbios {
U32 bus;
U32 slot;
} xgi_ioctl_post_vbios_t;
typedef enum xgi_mem_location_s
{
NON_LOCAL = 0,
LOCAL = 1,
INVALID = 0x7fffffff
} xgi_mem_location_t;
enum PcieOwner
{
PCIE_2D = 0,
/*
PCIE_3D should not begin with 1,
2D alloc pcie memory will use owner 1.
*/
PCIE_3D = 11,/*vetex buf*/
PCIE_3D_CMDLIST = 12,
PCIE_3D_SCRATCHPAD = 13,
PCIE_3D_TEXTURE = 14,
PCIE_INVALID = 0x7fffffff
};
typedef struct xgi_mem_req_s {
xgi_mem_location_t location;
unsigned long size;
unsigned long is_front;
enum PcieOwner owner;
unsigned long pid;
} xgi_mem_req_t;
typedef struct xgi_mem_alloc_s {
xgi_mem_location_t location;
unsigned long size;
unsigned long bus_addr;
unsigned long hw_addr;
unsigned long pid;
} xgi_mem_alloc_t;
typedef struct xgi_chip_info_s {
U32 device_id;
char device_name[32];
U32 vendor_id;
U32 curr_display_mode; //Singe, DualView(Contained), MHS
U32 fb_size;
U32 sarea_bus_addr;
U32 sarea_size;
} xgi_chip_info_t;
typedef struct xgi_opengl_cmd_s {
U32 cmd;
} xgi_opengl_cmd_t;
typedef struct xgi_mmio_info_s {
xgi_opengl_cmd_t cmd_head;
void *mmioBase;
int size;
} xgi_mmio_info_t;
typedef enum {
BTYPE_2D = 0,
BTYPE_3D = 1,
BTYPE_FLIP = 2,
BTYPE_CTRL = 3,
BTYPE_NONE = 0x7fffffff
}BATCH_TYPE;
typedef struct xgi_cmd_info_s {
BATCH_TYPE _firstBeginType;
U32 _firstBeginAddr;
U32 _firstSize;
U32 _curDebugID;
U32 _lastBeginAddr;
U32 _beginCount;
} xgi_cmd_info_t;
typedef struct xgi_state_info_s {
U32 _fromState;
U32 _toState;
} xgi_state_info_t;
typedef struct cpu_info_s {
U32 _eax;
U32 _ebx;
U32 _ecx;
U32 _edx;
} cpu_info_t;
typedef struct xgi_mem_pid_s {
struct list_head list;
xgi_mem_location_t location;
unsigned long bus_addr;
unsigned long pid;
} xgi_mem_pid_t;
/*
* Ioctl definitions
*/
#define XGI_IOCTL_MAGIC 'x' /* use 'x' as magic number */
#define XGI_IOCTL_BASE 0
#define XGI_ESC_DEVICE_INFO (XGI_IOCTL_BASE + 0)
#define XGI_ESC_POST_VBIOS (XGI_IOCTL_BASE + 1)
#define XGI_ESC_FB_INIT (XGI_IOCTL_BASE + 2)
#define XGI_ESC_FB_ALLOC (XGI_IOCTL_BASE + 3)
#define XGI_ESC_FB_FREE (XGI_IOCTL_BASE + 4)
#define XGI_ESC_PCIE_INIT (XGI_IOCTL_BASE + 5)
#define XGI_ESC_PCIE_ALLOC (XGI_IOCTL_BASE + 6)
#define XGI_ESC_PCIE_FREE (XGI_IOCTL_BASE + 7)
#define XGI_ESC_SUBMIT_CMDLIST (XGI_IOCTL_BASE + 8)
#define XGI_ESC_PUT_SCREEN_INFO (XGI_IOCTL_BASE + 9)
#define XGI_ESC_GET_SCREEN_INFO (XGI_IOCTL_BASE + 10)
#define XGI_ESC_GE_RESET (XGI_IOCTL_BASE + 11)
#define XGI_ESC_SAREA_INFO (XGI_IOCTL_BASE + 12)
#define XGI_ESC_DUMP_REGISTER (XGI_IOCTL_BASE + 13)
#define XGI_ESC_DEBUG_INFO (XGI_IOCTL_BASE + 14)
#define XGI_ESC_TEST_RWINKERNEL (XGI_IOCTL_BASE + 16)
#define XGI_ESC_STATE_CHANGE (XGI_IOCTL_BASE + 17)
#define XGI_ESC_MMIO_INFO (XGI_IOCTL_BASE + 18)
#define XGI_ESC_PCIE_CHECK (XGI_IOCTL_BASE + 19)
#define XGI_ESC_CPUID (XGI_IOCTL_BASE + 20)
#define XGI_ESC_MEM_COLLECT (XGI_IOCTL_BASE + 21)
#define XGI_IOCTL_DEVICE_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_DEVICE_INFO, xgi_chip_info_t)
#define XGI_IOCTL_POST_VBIOS _IO(XGI_IOCTL_MAGIC, XGI_ESC_POST_VBIOS)
#define XGI_IOCTL_FB_INIT _IO(XGI_IOCTL_MAGIC, XGI_ESC_FB_INIT)
#define XGI_IOCTL_FB_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_FB_ALLOC, xgi_mem_req_t)
#define XGI_IOCTL_FB_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_FB_FREE, unsigned long)
#define XGI_IOCTL_PCIE_INIT _IO(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_INIT)
#define XGI_IOCTL_PCIE_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_ALLOC, xgi_mem_req_t)
#define XGI_IOCTL_PCIE_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_FREE, unsigned long)
#define XGI_IOCTL_PUT_SCREEN_INFO _IOW(XGI_IOCTL_MAGIC, XGI_ESC_PUT_SCREEN_INFO, xgi_screen_info_t)
#define XGI_IOCTL_GET_SCREEN_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_GET_SCREEN_INFO, xgi_screen_info_t)
#define XGI_IOCTL_GE_RESET _IO(XGI_IOCTL_MAGIC, XGI_ESC_GE_RESET)
#define XGI_IOCTL_SAREA_INFO _IOW(XGI_IOCTL_MAGIC, XGI_ESC_SAREA_INFO, xgi_sarea_info_t)
#define XGI_IOCTL_DUMP_REGISTER _IO(XGI_IOCTL_MAGIC, XGI_ESC_DUMP_REGISTER)
#define XGI_IOCTL_DEBUG_INFO _IO(XGI_IOCTL_MAGIC, XGI_ESC_DEBUG_INFO)
#define XGI_IOCTL_MMIO_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_MMIO_INFO, xgi_mmio_info_t)
#define XGI_IOCTL_SUBMIT_CMDLIST _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_SUBMIT_CMDLIST, xgi_cmd_info_t)
#define XGI_IOCTL_TEST_RWINKERNEL _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_TEST_RWINKERNEL, unsigned long)
#define XGI_IOCTL_STATE_CHANGE _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_STATE_CHANGE, xgi_state_info_t)
#define XGI_IOCTL_PCIE_CHECK _IO(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_CHECK)
#define XGI_IOCTL_CPUID _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_CPUID, cpu_info_t)
#define XGI_IOCTL_MAXNR 30
/*
* flags
*/
#define XGI_FLAG_OPEN 0x0001
#define XGI_FLAG_NEEDS_POSTING 0x0002
#define XGI_FLAG_WAS_POSTED 0x0004
#define XGI_FLAG_CONTROL 0x0010
#define XGI_FLAG_MAP_REGS_EARLY 0x0200
/* mmap(2) offsets */
#define IS_IO_OFFSET(info, offset, length) \
(((offset) >= (info)->mmio.base) \
&& (((offset) + (length)) <= (info)->mmio.base + (info)->mmio.size))
/* Jong 06/14/2006 */
/* (info)->fb.base is a base address for physical (bus) address space */
/* what's the definition of offest? on physical (bus) address space or HW address space */
/* Jong 06/15/2006; use HW address space */
#define IS_FB_OFFSET(info, offset, length) \
(((offset) >= 0) \
&& (((offset) + (length)) <= (info)->fb.size))
#if 0
#define IS_FB_OFFSET(info, offset, length) \
(((offset) >= (info)->fb.base) \
&& (((offset) + (length)) <= (info)->fb.base + (info)->fb.size))
#endif
#define IS_PCIE_OFFSET(info, offset, length) \
(((offset) >= (info)->pcie.base) \
&& (((offset) + (length)) <= (info)->pcie.base + (info)->pcie.size))
extern int xgi_fb_heap_init(xgi_info_t *info);
extern void xgi_fb_heap_cleanup(xgi_info_t *info);
extern void xgi_fb_alloc(xgi_info_t *info, xgi_mem_req_t *req, xgi_mem_alloc_t *alloc);
extern void xgi_fb_free(xgi_info_t *info, unsigned long offset);
extern void xgi_mem_collect(xgi_info_t *info, unsigned int *pcnt);
extern int xgi_pcie_heap_init(xgi_info_t *info);
extern void xgi_pcie_heap_cleanup(xgi_info_t *info);
extern void xgi_pcie_alloc(xgi_info_t *info, unsigned long size, enum PcieOwner owner, xgi_mem_alloc_t *alloc);
extern void xgi_pcie_free(xgi_info_t *info, unsigned long offset);
extern void xgi_pcie_heap_check(void);
extern void *xgi_find_pcie_block(xgi_info_t *info, unsigned long address);
extern void *xgi_find_pcie_virt(xgi_info_t *info, unsigned long address);
extern void xgi_read_pcie_mem(xgi_info_t *info, xgi_mem_req_t *req);
extern void xgi_write_pcie_mem(xgi_info_t *info, xgi_mem_req_t *req);
extern void xgi_test_rwinkernel(xgi_info_t *info, unsigned long address);
#endif
/****************************************************************************
* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
* *
* All Rights Reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
* *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
***************************************************************************/
#ifndef _XGI_DRV_H_
#define _XGI_DRV_H_
#define XGI_MAJOR_VERSION 0
#define XGI_MINOR_VERSION 7
#define XGI_PATCHLEVEL 5
#define XGI_DRV_VERSION "0.7.5"
#ifndef XGI_DRV_NAME
#define XGI_DRV_NAME "xgi"
#endif
/*
* xgi reserved major device number, Set this to 0 to
* request dynamic major number allocation.
*/
#ifndef XGI_DEV_MAJOR
#define XGI_DEV_MAJOR 0
#endif
#ifndef XGI_MAX_DEVICES
#define XGI_MAX_DEVICES 1
#endif
/* Jong 06/06/2006 */
/* #define XGI_DEBUG */
#ifndef PCI_VENDOR_ID_XGI
/*
#define PCI_VENDOR_ID_XGI 0x1023
*/
#define PCI_VENDOR_ID_XGI 0x18CA
#endif
#ifndef PCI_DEVICE_ID_XP5
#define PCI_DEVICE_ID_XP5 0x2200
#endif
#ifndef PCI_DEVICE_ID_XG47
#define PCI_DEVICE_ID_XG47 0x0047
#endif
/* Macros to make printk easier */
#define XGI_ERROR(fmt, arg...) \
printk(KERN_ERR "[" XGI_DRV_NAME ":%s] *ERROR* " fmt, __FUNCTION__, ##arg)
#define XGI_MEM_ERROR(area, fmt, arg...) \
printk(KERN_ERR "[" XGI_DRV_NAME ":%s] *ERROR* " fmt, __FUNCTION__, ##arg)
/* #define XGI_DEBUG */
#ifdef XGI_DEBUG
#define XGI_INFO(fmt, arg...) \
printk(KERN_ALERT "[" XGI_DRV_NAME ":%s] " fmt, __FUNCTION__, ##arg)
/* printk(KERN_INFO "[" XGI_DRV_NAME ":%s] " fmt, __FUNCTION__, ##arg) */
#else
#define XGI_INFO(fmt, arg...) do { } while (0)
#endif
/* device name length; must be atleast 8 */
#define XGI_DEVICE_NAME_LENGTH 40
/* need a fake device number for control device; just to flag it for msgs */
#define XGI_CONTROL_DEVICE_NUMBER 100
typedef struct {
U32 base; // pcie base is different from fb base
U32 size;
U8 *vbase;
} xgi_aperture_t;
typedef struct xgi_screen_info_s {
U32 scrn_start;
U32 scrn_xres;
U32 scrn_yres;
U32 scrn_bpp;
U32 scrn_pitch;
} xgi_screen_info_t;
typedef struct xgi_sarea_info_s {
U32 bus_addr;
U32 size;
} xgi_sarea_info_t;
typedef struct xgi_info_s {
struct pci_dev *dev;
int flags;
int device_number;
int bus; /* PCI config info */
int slot;
int vendor_id;
U32 device_id;
U8 revision_id;
/* physical characteristics */
xgi_aperture_t mmio;
xgi_aperture_t fb;
xgi_aperture_t pcie;
xgi_screen_info_t scrn_info;
xgi_sarea_info_t sarea_info;
/* look up table parameters */
U32 *lut_base;
U32 lutPageSize;
U32 lutPageOrder;
U32 isLUTInLFB;
U32 sdfbPageSize;
U32 pcie_config;
U32 pcie_status;
U32 irq;
atomic_t use_count;
/* keep track of any pending bottom halfes */
struct tasklet_struct tasklet;
spinlock_t info_lock;
struct semaphore info_sem;
struct semaphore fb_sem;
struct semaphore pcie_sem;
} xgi_info_t;
typedef struct xgi_ioctl_post_vbios {
U32 bus;
U32 slot;
} xgi_ioctl_post_vbios_t;
typedef enum xgi_mem_location_s {
NON_LOCAL = 0,
LOCAL = 1,
INVALID = 0x7fffffff
} xgi_mem_location_t;
enum PcieOwner {
PCIE_2D = 0,
/*
PCIE_3D should not begin with 1,
2D alloc pcie memory will use owner 1.
*/
PCIE_3D = 11, /*vetex buf */
PCIE_3D_CMDLIST = 12,
PCIE_3D_SCRATCHPAD = 13,
PCIE_3D_TEXTURE = 14,
PCIE_INVALID = 0x7fffffff
};
typedef struct xgi_mem_req_s {
xgi_mem_location_t location;
unsigned long size;
unsigned long is_front;
enum PcieOwner owner;
unsigned long pid;
} xgi_mem_req_t;
typedef struct xgi_mem_alloc_s {
xgi_mem_location_t location;
unsigned long size;
unsigned long bus_addr;
unsigned long hw_addr;
unsigned long pid;
} xgi_mem_alloc_t;
typedef struct xgi_chip_info_s {
U32 device_id;
char device_name[32];
U32 vendor_id;
U32 curr_display_mode; //Singe, DualView(Contained), MHS
U32 fb_size;
U32 sarea_bus_addr;
U32 sarea_size;
} xgi_chip_info_t;
typedef struct xgi_opengl_cmd_s {
U32 cmd;
} xgi_opengl_cmd_t;
typedef struct xgi_mmio_info_s {
xgi_opengl_cmd_t cmd_head;
void *mmioBase;
int size;
} xgi_mmio_info_t;
typedef enum {
BTYPE_2D = 0,
BTYPE_3D = 1,
BTYPE_FLIP = 2,
BTYPE_CTRL = 3,
BTYPE_NONE = 0x7fffffff
} BATCH_TYPE;
typedef struct xgi_cmd_info_s {
BATCH_TYPE _firstBeginType;
U32 _firstBeginAddr;
U32 _firstSize;
U32 _curDebugID;
U32 _lastBeginAddr;
U32 _beginCount;
} xgi_cmd_info_t;
typedef struct xgi_state_info_s {
U32 _fromState;
U32 _toState;
} xgi_state_info_t;
typedef struct cpu_info_s {
U32 _eax;
U32 _ebx;
U32 _ecx;
U32 _edx;
} cpu_info_t;
typedef struct xgi_mem_pid_s {
struct list_head list;
xgi_mem_location_t location;
unsigned long bus_addr;
unsigned long pid;
} xgi_mem_pid_t;
/*
* Ioctl definitions
*/
#define XGI_IOCTL_MAGIC 'x' /* use 'x' as magic number */
#define XGI_IOCTL_BASE 0
#define XGI_ESC_DEVICE_INFO (XGI_IOCTL_BASE + 0)
#define XGI_ESC_POST_VBIOS (XGI_IOCTL_BASE + 1)
#define XGI_ESC_FB_INIT (XGI_IOCTL_BASE + 2)
#define XGI_ESC_FB_ALLOC (XGI_IOCTL_BASE + 3)
#define XGI_ESC_FB_FREE (XGI_IOCTL_BASE + 4)
#define XGI_ESC_PCIE_INIT (XGI_IOCTL_BASE + 5)
#define XGI_ESC_PCIE_ALLOC (XGI_IOCTL_BASE + 6)
#define XGI_ESC_PCIE_FREE (XGI_IOCTL_BASE + 7)
#define XGI_ESC_SUBMIT_CMDLIST (XGI_IOCTL_BASE + 8)
#define XGI_ESC_PUT_SCREEN_INFO (XGI_IOCTL_BASE + 9)
#define XGI_ESC_GET_SCREEN_INFO (XGI_IOCTL_BASE + 10)
#define XGI_ESC_GE_RESET (XGI_IOCTL_BASE + 11)
#define XGI_ESC_SAREA_INFO (XGI_IOCTL_BASE + 12)
#define XGI_ESC_DUMP_REGISTER (XGI_IOCTL_BASE + 13)
#define XGI_ESC_DEBUG_INFO (XGI_IOCTL_BASE + 14)
#define XGI_ESC_TEST_RWINKERNEL (XGI_IOCTL_BASE + 16)
#define XGI_ESC_STATE_CHANGE (XGI_IOCTL_BASE + 17)
#define XGI_ESC_MMIO_INFO (XGI_IOCTL_BASE + 18)
#define XGI_ESC_PCIE_CHECK (XGI_IOCTL_BASE + 19)
#define XGI_ESC_CPUID (XGI_IOCTL_BASE + 20)
#define XGI_ESC_MEM_COLLECT (XGI_IOCTL_BASE + 21)
#define XGI_IOCTL_DEVICE_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_DEVICE_INFO, xgi_chip_info_t)
#define XGI_IOCTL_POST_VBIOS _IO(XGI_IOCTL_MAGIC, XGI_ESC_POST_VBIOS)
#define XGI_IOCTL_FB_INIT _IO(XGI_IOCTL_MAGIC, XGI_ESC_FB_INIT)
#define XGI_IOCTL_FB_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_FB_ALLOC, xgi_mem_req_t)
#define XGI_IOCTL_FB_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_FB_FREE, unsigned long)
#define XGI_IOCTL_PCIE_INIT _IO(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_INIT)
#define XGI_IOCTL_PCIE_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_ALLOC, xgi_mem_req_t)
#define XGI_IOCTL_PCIE_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_FREE, unsigned long)
#define XGI_IOCTL_PUT_SCREEN_INFO _IOW(XGI_IOCTL_MAGIC, XGI_ESC_PUT_SCREEN_INFO, xgi_screen_info_t)
#define XGI_IOCTL_GET_SCREEN_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_GET_SCREEN_INFO, xgi_screen_info_t)
#define XGI_IOCTL_GE_RESET _IO(XGI_IOCTL_MAGIC, XGI_ESC_GE_RESET)
#define XGI_IOCTL_SAREA_INFO _IOW(XGI_IOCTL_MAGIC, XGI_ESC_SAREA_INFO, xgi_sarea_info_t)
#define XGI_IOCTL_DUMP_REGISTER _IO(XGI_IOCTL_MAGIC, XGI_ESC_DUMP_REGISTER)
#define XGI_IOCTL_DEBUG_INFO _IO(XGI_IOCTL_MAGIC, XGI_ESC_DEBUG_INFO)
#define XGI_IOCTL_MMIO_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_MMIO_INFO, xgi_mmio_info_t)
#define XGI_IOCTL_SUBMIT_CMDLIST _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_SUBMIT_CMDLIST, xgi_cmd_info_t)
#define XGI_IOCTL_TEST_RWINKERNEL _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_TEST_RWINKERNEL, unsigned long)
#define XGI_IOCTL_STATE_CHANGE _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_STATE_CHANGE, xgi_state_info_t)
#define XGI_IOCTL_PCIE_CHECK _IO(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_CHECK)
#define XGI_IOCTL_CPUID _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_CPUID, cpu_info_t)
#define XGI_IOCTL_MAXNR 30
/*
* flags
*/
#define XGI_FLAG_OPEN 0x0001
#define XGI_FLAG_NEEDS_POSTING 0x0002
#define XGI_FLAG_WAS_POSTED 0x0004
#define XGI_FLAG_CONTROL 0x0010
#define XGI_FLAG_MAP_REGS_EARLY 0x0200
/* mmap(2) offsets */
#define IS_IO_OFFSET(info, offset, length) \
(((offset) >= (info)->mmio.base) \
&& (((offset) + (length)) <= (info)->mmio.base + (info)->mmio.size))
/* Jong 06/14/2006 */
/* (info)->fb.base is a base address for physical (bus) address space */
/* what's the definition of offest? on physical (bus) address space or HW address space */
/* Jong 06/15/2006; use HW address space */
#define IS_FB_OFFSET(info, offset, length) \
(((offset) >= 0) \
&& (((offset) + (length)) <= (info)->fb.size))
#if 0
#define IS_FB_OFFSET(info, offset, length) \
(((offset) >= (info)->fb.base) \
&& (((offset) + (length)) <= (info)->fb.base + (info)->fb.size))
#endif
#define IS_PCIE_OFFSET(info, offset, length) \
(((offset) >= (info)->pcie.base) \
&& (((offset) + (length)) <= (info)->pcie.base + (info)->pcie.size))
extern int xgi_fb_heap_init(xgi_info_t * info);
extern void xgi_fb_heap_cleanup(xgi_info_t * info);
extern void xgi_fb_alloc(xgi_info_t * info, xgi_mem_req_t * req,
xgi_mem_alloc_t * alloc);
extern void xgi_fb_free(xgi_info_t * info, unsigned long offset);
extern void xgi_mem_collect(xgi_info_t * info, unsigned int *pcnt);
extern int xgi_pcie_heap_init(xgi_info_t * info);
extern void xgi_pcie_heap_cleanup(xgi_info_t * info);
extern void xgi_pcie_alloc(xgi_info_t * info, unsigned long size,
enum PcieOwner owner, xgi_mem_alloc_t * alloc);
extern void xgi_pcie_free(xgi_info_t * info, unsigned long offset);
extern void xgi_pcie_heap_check(void);
extern void *xgi_find_pcie_block(xgi_info_t * info, unsigned long address);
extern void *xgi_find_pcie_virt(xgi_info_t * info, unsigned long address);
extern void xgi_read_pcie_mem(xgi_info_t * info, xgi_mem_req_t * req);
extern void xgi_write_pcie_mem(xgi_info_t * info, xgi_mem_req_t * req);
extern void xgi_test_rwinkernel(xgi_info_t * info, unsigned long address);
#endif

1019
linux-core/xgi_fb.c
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linux-core/xgi_fb.h
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/****************************************************************************
* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
* *
* All Rights Reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
* *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
***************************************************************************/
#ifndef _XGI_FB_H_
#define _XGI_FB_H_
typedef struct xgi_mem_block_s {
struct list_head list;
unsigned long offset;
unsigned long size;
atomic_t use_count;
} xgi_mem_block_t;
typedef struct xgi_mem_heap_s {
struct list_head free_list;
struct list_head used_list;
struct list_head sort_list;
unsigned long max_freesize;
spinlock_t lock;
} xgi_mem_heap_t;
#if 0
typedef struct xgi_mem_block_s {
struct xgi_mem_block_s *next;
struct xgi_mem_block_s *prev;
unsigned long offset;
unsigned long size;
atomic_t use_count;
} xgi_mem_block_t;
typedef struct xgi_mem_list_s {
xgi_mem_block_t *head;
xgi_mem_block_t *tail;
} xgi_mem_list_t;
typedef struct xgi_mem_heap_s {
xgi_mem_list_t *free_list;
xgi_mem_list_t *used_list;
xgi_mem_list_t *sort_list;
unsigned long max_freesize;
spinlock_t lock;
} xgi_mem_heap_t;
#endif
#endif
/****************************************************************************
* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
* *
* All Rights Reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
* *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
***************************************************************************/
#ifndef _XGI_FB_H_
#define _XGI_FB_H_
typedef struct xgi_mem_block_s {
struct list_head list;
unsigned long offset;
unsigned long size;
atomic_t use_count;
} xgi_mem_block_t;
typedef struct xgi_mem_heap_s {
struct list_head free_list;
struct list_head used_list;
struct list_head sort_list;
unsigned long max_freesize;
spinlock_t lock;
} xgi_mem_heap_t;
#if 0
typedef struct xgi_mem_block_s {
struct xgi_mem_block_s *next;
struct xgi_mem_block_s *prev;
unsigned long offset;
unsigned long size;
atomic_t use_count;
} xgi_mem_block_t;
typedef struct xgi_mem_list_s {
xgi_mem_block_t *head;
xgi_mem_block_t *tail;
} xgi_mem_list_t;
typedef struct xgi_mem_heap_s {
xgi_mem_list_t *free_list;
xgi_mem_list_t *used_list;
xgi_mem_list_t *sort_list;
unsigned long max_freesize;
spinlock_t lock;
} xgi_mem_heap_t;
#endif
#endif

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linux-core/xgi_linux.h
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linux-core/xgi_misc.c
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linux-core/xgi_misc.h
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/****************************************************************************
* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
* *
* All Rights Reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
* *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
***************************************************************************/
#ifndef _XGI_MISC_H_
#define _XGI_MISC_H_
extern void xgi_dump_register(xgi_info_t *info);
extern void xgi_get_device_info(xgi_info_t *info, xgi_chip_info_t * req);
extern void xgi_get_mmio_info(xgi_info_t *info, xgi_mmio_info_t *req);
extern void xgi_get_screen_info(xgi_info_t *info, xgi_screen_info_t *req);
extern void xgi_put_screen_info(xgi_info_t *info, xgi_screen_info_t *req);
extern void xgi_ge_reset(xgi_info_t *info);
extern void xgi_sarea_info(xgi_info_t *info, xgi_sarea_info_t *req);
extern int xgi_get_cpu_id(struct cpu_info_s *arg);
extern void xgi_restore_registers(xgi_info_t *info);
extern BOOL xgi_ge_irq_handler(xgi_info_t *info);
extern BOOL xgi_crt_irq_handler(xgi_info_t *info);
extern BOOL xgi_dvi_irq_handler(xgi_info_t *info);
extern void xgi_waitfor_pci_idle(xgi_info_t *info);
#endif
/****************************************************************************
* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
* *
* All Rights Reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
* *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
***************************************************************************/
#ifndef _XGI_MISC_H_
#define _XGI_MISC_H_
extern void xgi_dump_register(xgi_info_t * info);
extern void xgi_get_device_info(xgi_info_t * info, xgi_chip_info_t * req);
extern void xgi_get_mmio_info(xgi_info_t * info, xgi_mmio_info_t * req);
extern void xgi_get_screen_info(xgi_info_t * info, xgi_screen_info_t * req);
extern void xgi_put_screen_info(xgi_info_t * info, xgi_screen_info_t * req);
extern void xgi_ge_reset(xgi_info_t * info);
extern void xgi_sarea_info(xgi_info_t * info, xgi_sarea_info_t * req);
extern int xgi_get_cpu_id(struct cpu_info_s *arg);
extern void xgi_restore_registers(xgi_info_t * info);
extern BOOL xgi_ge_irq_handler(xgi_info_t * info);
extern BOOL xgi_crt_irq_handler(xgi_info_t * info);
extern BOOL xgi_dvi_irq_handler(xgi_info_t * info);
extern void xgi_waitfor_pci_idle(xgi_info_t * info);
#endif

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linux-core/xgi_pcie.c
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linux-core/xgi_pcie.h
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/****************************************************************************
* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
* *
* All Rights Reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
* *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
***************************************************************************/
#ifndef _XGI_PCIE_H_
#define _XGI_PCIE_H_
#ifndef XGI_PCIE_ALLOC_MAX_ORDER
#define XGI_PCIE_ALLOC_MAX_ORDER 1 /* 8K in Kernel 2.4.* */
#endif
typedef struct xgi_page_block_s {
struct xgi_page_block_s *next;
unsigned long phys_addr;
unsigned long virt_addr;
unsigned long page_count;
unsigned long page_order;
} xgi_page_block_t;
typedef struct xgi_pcie_block_s {
struct list_head list;
unsigned long offset; /* block's offset in pcie memory, begin from 0 */
unsigned long size; /* The block size. */
unsigned long bus_addr; /* CPU access address/bus address */
unsigned long hw_addr; /* GE access address */
unsigned long page_count;
unsigned long page_order;
xgi_page_block_t *page_block;
xgi_pte_t *page_table; /* list of physical pages allocated */
atomic_t use_count;
enum PcieOwner owner;
unsigned long processID;
} xgi_pcie_block_t;
typedef struct xgi_pcie_list_s {
xgi_pcie_block_t *head;
xgi_pcie_block_t *tail;
} xgi_pcie_list_t;
typedef struct xgi_pcie_heap_s {
struct list_head free_list;
struct list_head used_list;
struct list_head sort_list;
unsigned long max_freesize;
} xgi_pcie_heap_t;
#endif
/****************************************************************************
* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
* *
* All Rights Reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
* *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
***************************************************************************/
#ifndef _XGI_PCIE_H_
#define _XGI_PCIE_H_
#ifndef XGI_PCIE_ALLOC_MAX_ORDER
#define XGI_PCIE_ALLOC_MAX_ORDER 1 /* 8K in Kernel 2.4.* */
#endif
typedef struct xgi_page_block_s {
struct xgi_page_block_s *next;
unsigned long phys_addr;
unsigned long virt_addr;
unsigned long page_count;
unsigned long page_order;
} xgi_page_block_t;
typedef struct xgi_pcie_block_s {
struct list_head list;
unsigned long offset; /* block's offset in pcie memory, begin from 0 */
unsigned long size; /* The block size. */
unsigned long bus_addr; /* CPU access address/bus address */
unsigned long hw_addr; /* GE access address */
unsigned long page_count;
unsigned long page_order;
xgi_page_block_t *page_block;
xgi_pte_t *page_table; /* list of physical pages allocated */
atomic_t use_count;
enum PcieOwner owner;
unsigned long processID;
} xgi_pcie_block_t;
typedef struct xgi_pcie_list_s {
xgi_pcie_block_t *head;
xgi_pcie_block_t *tail;
} xgi_pcie_list_t;
typedef struct xgi_pcie_heap_s {
struct list_head free_list;
struct list_head used_list;
struct list_head sort_list;
unsigned long max_freesize;
} xgi_pcie_heap_t;
#endif

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linux-core/xgi_regs.h
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/****************************************************************************
* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
* *
* All Rights Reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
* *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
***************************************************************************/
#ifndef _XGI_REGS_H_
#define _XGI_REGS_H_
#ifndef XGI_MMIO
#define XGI_MMIO 1
#endif
#if XGI_MMIO
#define OUTB(port, value) writeb(value, info->mmio.vbase + port)
#define INB(port) readb(info->mmio.vbase + port)
#define OUTW(port, value) writew(value, info->mmio.vbase + port)
#define INW(port) readw(info->mmio.vbase + port)
#define OUTDW(port, value) writel(value, info->mmio.vbase + port)
#define INDW(port) readl(info->mmio.vbase + port)
#else
#define OUTB(port, value) outb(value, port)
#define INB(port) inb(port)
#define OUTW(port, value) outw(value, port)
#define INW(port) inw(port)
#define OUTDW(port, value) outl(value, port)
#define INDW(port) inl(port)
#endif
/* Hardware access functions */
static inline void OUT3C5B(xgi_info_t *info, u8 index, u8 data)
{
OUTB(0x3C4, index);
OUTB(0x3C5, data);
}
static inline void OUT3X5B(xgi_info_t *info, u8 index, u8 data)
{
OUTB(0x3D4, index);
OUTB(0x3D5, data);
}
static inline void OUT3CFB(xgi_info_t *info, u8 index, u8 data)
{
OUTB(0x3CE, index);
OUTB(0x3CF, data);
}
static inline u8 IN3C5B(xgi_info_t *info, u8 index)
{
volatile u8 data=0;
OUTB(0x3C4, index);
data = INB(0x3C5);
return data;
}
static inline u8 IN3X5B(xgi_info_t *info, u8 index)
{
volatile u8 data=0;
OUTB(0x3D4, index);
data = INB(0x3D5);
return data;
}
static inline u8 IN3CFB(xgi_info_t *info, u8 index)
{
volatile u8 data=0;
OUTB(0x3CE, index);
data = INB(0x3CF);
return data;
}
static inline void OUT3C5W(xgi_info_t *info, u8 index, u16 data)
{
OUTB(0x3C4, index);
OUTB(0x3C5, data);
}
static inline void OUT3X5W(xgi_info_t *info, u8 index, u16 data)
{
OUTB(0x3D4, index);
OUTB(0x3D5, data);
}
static inline void OUT3CFW(xgi_info_t *info, u8 index, u8 data)
{
OUTB(0x3CE, index);
OUTB(0x3CF, data);
}
static inline u8 IN3C5W(xgi_info_t *info, u8 index)
{
volatile u8 data=0;
OUTB(0x3C4, index);
data = INB(0x3C5);
return data;
}
static inline u8 IN3X5W(xgi_info_t *info, u8 index)
{
volatile u8 data=0;
OUTB(0x3D4, index);
data = INB(0x3D5);
return data;
}
static inline u8 IN3CFW(xgi_info_t *info, u8 index)
{
volatile u8 data=0;
OUTB(0x3CE, index);
data = INB(0x3CF);
return data;
}
static inline u8 readAttr(xgi_info_t *info, u8 index)
{
INB(0x3DA); /* flip-flop to index */
OUTB(0x3C0, index);
return INB(0x3C1);
}
static inline void writeAttr(xgi_info_t *info, u8 index, u8 value)
{
INB(0x3DA); /* flip-flop to index */
OUTB(0x3C0, index);
OUTB(0x3C0, value);
}
/*
* Graphic engine register (2d/3d) acessing interface
*/
static inline void WriteRegDWord(xgi_info_t *info, u32 addr, u32 data)
{
/* Jong 05/25/2006 */
XGI_INFO("Jong-WriteRegDWord()-Begin \n");
XGI_INFO("Jong-WriteRegDWord()-info->mmio.vbase=0x%lx \n", info->mmio.vbase);
XGI_INFO("Jong-WriteRegDWord()-addr=0x%lx \n", addr);
XGI_INFO("Jong-WriteRegDWord()-data=0x%lx \n", data);
/* return; */
*(volatile u32*)(info->mmio.vbase + addr) = (data);
XGI_INFO("Jong-WriteRegDWord()-End \n");
}
static inline void WriteRegWord(xgi_info_t *info, u32 addr, u16 data)
{
*(volatile u16*)(info->mmio.vbase + addr) = (data);
}
static inline void WriteRegByte(xgi_info_t *info, u32 addr, u8 data)
{
*(volatile u8*)(info->mmio.vbase + addr) = (data);
}
static inline u32 ReadRegDWord(xgi_info_t *info, u32 addr)
{
volatile u32 data;
data = *(volatile u32*)(info->mmio.vbase + addr);
return data;
}
static inline u16 ReadRegWord(xgi_info_t *info, u32 addr)
{
volatile u16 data;
data = *(volatile u16*)(info->mmio.vbase + addr);
return data;
}
static inline u8 ReadRegByte(xgi_info_t *info, u32 addr)
{
volatile u8 data;
data = *(volatile u8*)(info->mmio.vbase + addr);
return data;
}
#if 0
extern void OUT3C5B(xgi_info_t *info, u8 index, u8 data);
extern void OUT3X5B(xgi_info_t *info, u8 index, u8 data);
extern void OUT3CFB(xgi_info_t *info, u8 index, u8 data);
extern u8 IN3C5B(xgi_info_t *info, u8 index);
extern u8 IN3X5B(xgi_info_t *info, u8 index);
extern u8 IN3CFB(xgi_info_t *info, u8 index);
extern void OUT3C5W(xgi_info_t *info, u8 index, u8 data);
extern void OUT3X5W(xgi_info_t *info, u8 index, u8 data);
extern void OUT3CFW(xgi_info_t *info, u8 index, u8 data);
extern u8 IN3C5W(xgi_info_t *info, u8 index);
extern u8 IN3X5W(xgi_info_t *info, u8 index);
extern u8 IN3CFW(xgi_info_t *info, u8 index);
extern void WriteRegDWord(xgi_info_t *info, u32 addr, u32 data);
extern void WriteRegWord(xgi_info_t *info, u32 addr, u16 data);
extern void WriteRegByte(xgi_info_t *info, u32 addr, u8 data);
extern u32 ReadRegDWord(xgi_info_t *info, u32 addr);
extern u16 ReadRegWord(xgi_info_t *info, u32 addr);
extern u8 ReadRegByte(xgi_info_t *info, u32 addr);
extern void EnableProtect();
extern void DisableProtect();
#endif
#define Out(port, data) OUTB(port, data)
#define bOut(port, data) OUTB(port, data)
#define wOut(port, data) OUTW(port, data)
#define dwOut(port, data) OUTDW(port, data)
#define Out3x5(index, data) OUT3X5B(info, index, data)
#define bOut3x5(index, data) OUT3X5B(info, index, data)
#define wOut3x5(index, data) OUT3X5W(info, index, data)
#define Out3c5(index, data) OUT3C5B(info, index, data)
#define bOut3c5(index, data) OUT3C5B(info, index, data)
#define wOut3c5(index, data) OUT3C5W(info, index, data)
#define Out3cf(index, data) OUT3CFB(info, index, data)
#define bOut3cf(index, data) OUT3CFB(info, index, data)
#define wOut3cf(index, data) OUT3CFW(info, index, data)
#define In(port) INB(port)
#define bIn(port) INB(port)
#define wIn(port) INW(port)
#define dwIn(port) INDW(port)
#define In3x5(index) IN3X5B(info, index)
#define bIn3x5(index) IN3X5B(info, index)
#define wIn3x5(index) IN3X5W(info, index)
#define In3c5(index) IN3C5B(info, index)
#define bIn3c5(index) IN3C5B(info, index)
#define wIn3c5(index) IN3C5W(info, index)
#define In3cf(index) IN3CFB(info, index)
#define bIn3cf(index) IN3CFB(info, index)
#define wIn3cf(index) IN3CFW(info, index)
#define dwWriteReg(addr, data) WriteRegDWord(info, addr, data)
#define wWriteReg(addr, data) WriteRegWord(info, addr, data)
#define bWriteReg(addr, data) WriteRegByte(info, addr, data)
#define dwReadReg(addr) ReadRegDWord(info, addr)
#define wReadReg(addr) ReadRegWord(info, addr)
#define bReadReg(addr) ReadRegByte(info, addr)
static inline void xgi_protect_all(xgi_info_t *info)
{
OUTB(0x3C4, 0x11);
OUTB(0x3C5, 0x92);
}
static inline void xgi_unprotect_all(xgi_info_t *info)
{
OUTB(0x3C4, 0x11);
OUTB(0x3C5, 0x92);
}
static inline void xgi_enable_mmio(xgi_info_t *info)
{
u8 protect = 0;
/* Unprotect registers */
outb(0x11, 0x3C4);
protect = inb(0x3C5);
outb(0x92, 0x3C5);
outb(0x3A, 0x3D4);
outb(inb(0x3D5) | 0x20, 0x3D5);
/* Enable MMIO */
outb(0x39, 0x3D4);
outb(inb(0x3D5) | 0x01, 0x3D5);
OUTB(0x3C4, 0x11);
OUTB(0x3C5, protect);
}
static inline void xgi_disable_mmio(xgi_info_t *info)
{
u8 protect = 0;
/* unprotect registers */
OUTB(0x3C4, 0x11);
protect = INB(0x3C5);
OUTB(0x3C5, 0x92);
/* Disable MMIO access */
OUTB(0x3D4, 0x39);
OUTB(0x3D5, INB(0x3D5) & 0xFE);
/* Protect registers */
outb(0x11, 0x3C4);
outb(protect, 0x3C5);
}
static inline void xgi_enable_ge(xgi_info_t *info)
{
unsigned char bOld3cf2a = 0;
int wait = 0;
// Enable GE
OUTW(0x3C4, 0x9211);
// Save and close dynamic gating
bOld3cf2a = bIn3cf(0x2a);
bOut3cf(0x2a, bOld3cf2a & 0xfe);
// Reset both 3D and 2D engine
bOut3x5(0x36, 0x84);
wait = 10;
while (wait--)
{
bIn(0x36);
}
bOut3x5(0x36, 0x94);
wait = 10;
while (wait--)
{
bIn(0x36);
}
bOut3x5(0x36, 0x84);
wait = 10;
while (wait--)
{
bIn(0x36);
}
// Enable 2D engine only
bOut3x5(0x36, 0x80);
// Enable 2D+3D engine
bOut3x5(0x36, 0x84);
// Restore dynamic gating
bOut3cf(0x2a, bOld3cf2a);
}
static inline void xgi_disable_ge(xgi_info_t *info)
{
int wait = 0;
// Reset both 3D and 2D engine
bOut3x5(0x36, 0x84);
wait = 10;
while (wait--)
{
bIn(0x36);
}
bOut3x5(0x36, 0x94);
wait = 10;
while (wait--)
{
bIn(0x36);
}
bOut3x5(0x36, 0x84);
wait = 10;
while (wait--)
{
bIn(0x36);
}
// Disable 2D engine only
bOut3x5(0x36, 0);
}
static inline void xgi_enable_dvi_interrupt(xgi_info_t *info)
{
Out3cf(0x39, In3cf(0x39) & ~0x01); //Set 3cf.39 bit 0 to 0
Out3cf(0x39, In3cf(0x39) | 0x01); //Set 3cf.39 bit 0 to 1
Out3cf(0x39, In3cf(0x39) | 0x02);
}
static inline void xgi_disable_dvi_interrupt(xgi_info_t *info)
{
Out3cf(0x39,In3cf(0x39) & ~0x02);
}
static inline void xgi_enable_crt1_interrupt(xgi_info_t *info)
{
Out3cf(0x3d,In3cf(0x3d) | 0x04);
Out3cf(0x3d,In3cf(0x3d) & ~0x04);
Out3cf(0x3d,In3cf(0x3d) | 0x08);
}
static inline void xgi_disable_crt1_interrupt(xgi_info_t *info)
{
Out3cf(0x3d,In3cf(0x3d) & ~0x08);
}
#endif
/****************************************************************************
* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
* *
* All Rights Reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
* *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
***************************************************************************/
#ifndef _XGI_REGS_H_
#define _XGI_REGS_H_
#ifndef XGI_MMIO
#define XGI_MMIO 1
#endif
#if XGI_MMIO
#define OUTB(port, value) writeb(value, info->mmio.vbase + port)
#define INB(port) readb(info->mmio.vbase + port)
#define OUTW(port, value) writew(value, info->mmio.vbase + port)
#define INW(port) readw(info->mmio.vbase + port)
#define OUTDW(port, value) writel(value, info->mmio.vbase + port)
#define INDW(port) readl(info->mmio.vbase + port)
#else
#define OUTB(port, value) outb(value, port)
#define INB(port) inb(port)
#define OUTW(port, value) outw(value, port)
#define INW(port) inw(port)
#define OUTDW(port, value) outl(value, port)
#define INDW(port) inl(port)
#endif
/* Hardware access functions */
static inline void OUT3C5B(xgi_info_t * info, u8 index, u8 data)
{
OUTB(0x3C4, index);
OUTB(0x3C5, data);
}
static inline void OUT3X5B(xgi_info_t * info, u8 index, u8 data)
{
OUTB(0x3D4, index);
OUTB(0x3D5, data);
}
static inline void OUT3CFB(xgi_info_t * info, u8 index, u8 data)
{
OUTB(0x3CE, index);
OUTB(0x3CF, data);
}
static inline u8 IN3C5B(xgi_info_t * info, u8 index)
{
volatile u8 data = 0;
OUTB(0x3C4, index);
data = INB(0x3C5);
return data;
}
static inline u8 IN3X5B(xgi_info_t * info, u8 index)
{
volatile u8 data = 0;
OUTB(0x3D4, index);
data = INB(0x3D5);
return data;
}
static inline u8 IN3CFB(xgi_info_t * info, u8 index)
{
volatile u8 data = 0;
OUTB(0x3CE, index);
data = INB(0x3CF);
return data;
}
static inline void OUT3C5W(xgi_info_t * info, u8 index, u16 data)
{
OUTB(0x3C4, index);
OUTB(0x3C5, data);
}
static inline void OUT3X5W(xgi_info_t * info, u8 index, u16 data)
{
OUTB(0x3D4, index);
OUTB(0x3D5, data);
}
static inline void OUT3CFW(xgi_info_t * info, u8 index, u8 data)
{
OUTB(0x3CE, index);
OUTB(0x3CF, data);
}
static inline u8 IN3C5W(xgi_info_t * info, u8 index)
{
volatile u8 data = 0;
OUTB(0x3C4, index);
data = INB(0x3C5);
return data;
}
static inline u8 IN3X5W(xgi_info_t * info, u8 index)
{
volatile u8 data = 0;
OUTB(0x3D4, index);
data = INB(0x3D5);
return data;
}
static inline u8 IN3CFW(xgi_info_t * info, u8 index)
{
volatile u8 data = 0;
OUTB(0x3CE, index);
data = INB(0x3CF);
return data;
}
static inline u8 readAttr(xgi_info_t * info, u8 index)
{
INB(0x3DA); /* flip-flop to index */
OUTB(0x3C0, index);
return INB(0x3C1);
}
static inline void writeAttr(xgi_info_t * info, u8 index, u8 value)
{
INB(0x3DA); /* flip-flop to index */
OUTB(0x3C0, index);
OUTB(0x3C0, value);
}
/*
* Graphic engine register (2d/3d) acessing interface
*/
static inline void WriteRegDWord(xgi_info_t * info, u32 addr, u32 data)
{
/* Jong 05/25/2006 */
XGI_INFO("Jong-WriteRegDWord()-Begin \n");
XGI_INFO("Jong-WriteRegDWord()-info->mmio.vbase=0x%lx \n",
info->mmio.vbase);
XGI_INFO("Jong-WriteRegDWord()-addr=0x%lx \n", addr);
XGI_INFO("Jong-WriteRegDWord()-data=0x%lx \n", data);
/* return; */
*(volatile u32 *)(info->mmio.vbase + addr) = (data);
XGI_INFO("Jong-WriteRegDWord()-End \n");
}
static inline void WriteRegWord(xgi_info_t * info, u32 addr, u16 data)
{
*(volatile u16 *)(info->mmio.vbase + addr) = (data);
}
static inline void WriteRegByte(xgi_info_t * info, u32 addr, u8 data)
{
*(volatile u8 *)(info->mmio.vbase + addr) = (data);
}
static inline u32 ReadRegDWord(xgi_info_t * info, u32 addr)
{
volatile u32 data;
data = *(volatile u32 *)(info->mmio.vbase + addr);
return data;
}
static inline u16 ReadRegWord(xgi_info_t * info, u32 addr)
{
volatile u16 data;
data = *(volatile u16 *)(info->mmio.vbase + addr);
return data;
}
static inline u8 ReadRegByte(xgi_info_t * info, u32 addr)
{
volatile u8 data;
data = *(volatile u8 *)(info->mmio.vbase + addr);
return data;
}
#if 0
extern void OUT3C5B(xgi_info_t * info, u8 index, u8 data);
extern void OUT3X5B(xgi_info_t * info, u8 index, u8 data);
extern void OUT3CFB(xgi_info_t * info, u8 index, u8 data);
extern u8 IN3C5B(xgi_info_t * info, u8 index);
extern u8 IN3X5B(xgi_info_t * info, u8 index);
extern u8 IN3CFB(xgi_info_t * info, u8 index);
extern void OUT3C5W(xgi_info_t * info, u8 index, u8 data);
extern void OUT3X5W(xgi_info_t * info, u8 index, u8 data);
extern void OUT3CFW(xgi_info_t * info, u8 index, u8 data);
extern u8 IN3C5W(xgi_info_t * info, u8 index);
extern u8 IN3X5W(xgi_info_t * info, u8 index);
extern u8 IN3CFW(xgi_info_t * info, u8 index);
extern void WriteRegDWord(xgi_info_t * info, u32 addr, u32 data);
extern void WriteRegWord(xgi_info_t * info, u32 addr, u16 data);
extern void WriteRegByte(xgi_info_t * info, u32 addr, u8 data);
extern u32 ReadRegDWord(xgi_info_t * info, u32 addr);
extern u16 ReadRegWord(xgi_info_t * info, u32 addr);
extern u8 ReadRegByte(xgi_info_t * info, u32 addr);
extern void EnableProtect();
extern void DisableProtect();
#endif
#define Out(port, data) OUTB(port, data)
#define bOut(port, data) OUTB(port, data)
#define wOut(port, data) OUTW(port, data)
#define dwOut(port, data) OUTDW(port, data)
#define Out3x5(index, data) OUT3X5B(info, index, data)
#define bOut3x5(index, data) OUT3X5B(info, index, data)
#define wOut3x5(index, data) OUT3X5W(info, index, data)
#define Out3c5(index, data) OUT3C5B(info, index, data)
#define bOut3c5(index, data) OUT3C5B(info, index, data)
#define wOut3c5(index, data) OUT3C5W(info, index, data)
#define Out3cf(index, data) OUT3CFB(info, index, data)
#define bOut3cf(index, data) OUT3CFB(info, index, data)
#define wOut3cf(index, data) OUT3CFW(info, index, data)
#define In(port) INB(port)
#define bIn(port) INB(port)
#define wIn(port) INW(port)
#define dwIn(port) INDW(port)
#define In3x5(index) IN3X5B(info, index)
#define bIn3x5(index) IN3X5B(info, index)
#define wIn3x5(index) IN3X5W(info, index)
#define In3c5(index) IN3C5B(info, index)
#define bIn3c5(index) IN3C5B(info, index)
#define wIn3c5(index) IN3C5W(info, index)
#define In3cf(index) IN3CFB(info, index)
#define bIn3cf(index) IN3CFB(info, index)
#define wIn3cf(index) IN3CFW(info, index)
#define dwWriteReg(addr, data) WriteRegDWord(info, addr, data)
#define wWriteReg(addr, data) WriteRegWord(info, addr, data)
#define bWriteReg(addr, data) WriteRegByte(info, addr, data)
#define dwReadReg(addr) ReadRegDWord(info, addr)
#define wReadReg(addr) ReadRegWord(info, addr)
#define bReadReg(addr) ReadRegByte(info, addr)
static inline void xgi_protect_all(xgi_info_t * info)
{
OUTB(0x3C4, 0x11);
OUTB(0x3C5, 0x92);
}
static inline void xgi_unprotect_all(xgi_info_t * info)
{
OUTB(0x3C4, 0x11);
OUTB(0x3C5, 0x92);
}
static inline void xgi_enable_mmio(xgi_info_t * info)
{
u8 protect = 0;
/* Unprotect registers */
outb(0x11, 0x3C4);
protect = inb(0x3C5);
outb(0x92, 0x3C5);
outb(0x3A, 0x3D4);
outb(inb(0x3D5) | 0x20, 0x3D5);
/* Enable MMIO */
outb(0x39, 0x3D4);
outb(inb(0x3D5) | 0x01, 0x3D5);
OUTB(0x3C4, 0x11);
OUTB(0x3C5, protect);
}
static inline void xgi_disable_mmio(xgi_info_t * info)
{
u8 protect = 0;
/* unprotect registers */
OUTB(0x3C4, 0x11);
protect = INB(0x3C5);
OUTB(0x3C5, 0x92);
/* Disable MMIO access */
OUTB(0x3D4, 0x39);
OUTB(0x3D5, INB(0x3D5) & 0xFE);
/* Protect registers */
outb(0x11, 0x3C4);
outb(protect, 0x3C5);
}
static inline void xgi_enable_ge(xgi_info_t * info)
{
unsigned char bOld3cf2a = 0;
int wait = 0;
// Enable GE
OUTW(0x3C4, 0x9211);
// Save and close dynamic gating
bOld3cf2a = bIn3cf(0x2a);
bOut3cf(0x2a, bOld3cf2a & 0xfe);
// Reset both 3D and 2D engine
bOut3x5(0x36, 0x84);
wait = 10;
while (wait--) {
bIn(0x36);
}
bOut3x5(0x36, 0x94);
wait = 10;
while (wait--) {
bIn(0x36);
}
bOut3x5(0x36, 0x84);
wait = 10;
while (wait--) {
bIn(0x36);
}
// Enable 2D engine only
bOut3x5(0x36, 0x80);
// Enable 2D+3D engine
bOut3x5(0x36, 0x84);
// Restore dynamic gating
bOut3cf(0x2a, bOld3cf2a);
}
static inline void xgi_disable_ge(xgi_info_t * info)
{
int wait = 0;
// Reset both 3D and 2D engine
bOut3x5(0x36, 0x84);
wait = 10;
while (wait--) {
bIn(0x36);
}
bOut3x5(0x36, 0x94);
wait = 10;
while (wait--) {
bIn(0x36);
}
bOut3x5(0x36, 0x84);
wait = 10;
while (wait--) {
bIn(0x36);
}
// Disable 2D engine only
bOut3x5(0x36, 0);
}
static inline void xgi_enable_dvi_interrupt(xgi_info_t * info)
{
Out3cf(0x39, In3cf(0x39) & ~0x01); //Set 3cf.39 bit 0 to 0
Out3cf(0x39, In3cf(0x39) | 0x01); //Set 3cf.39 bit 0 to 1
Out3cf(0x39, In3cf(0x39) | 0x02);
}
static inline void xgi_disable_dvi_interrupt(xgi_info_t * info)
{
Out3cf(0x39, In3cf(0x39) & ~0x02);
}
static inline void xgi_enable_crt1_interrupt(xgi_info_t * info)
{
Out3cf(0x3d, In3cf(0x3d) | 0x04);
Out3cf(0x3d, In3cf(0x3d) & ~0x04);
Out3cf(0x3d, In3cf(0x3d) | 0x08);
}
static inline void xgi_disable_crt1_interrupt(xgi_info_t * info)
{
Out3cf(0x3d, In3cf(0x3d) & ~0x08);
}
#endif

135
linux-core/xgi_types.h
View File

@ -1,68 +1,67 @@
/****************************************************************************
* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
* *
* All Rights Reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
* *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
***************************************************************************/
#ifndef _XGI_TYPES_H_
#define _XGI_TYPES_H_
/****************************************************************************
* Typedefs *
***************************************************************************/
typedef unsigned char V8; /* "void": enumerated or multiple fields */
typedef unsigned short V16; /* "void": enumerated or multiple fields */
typedef unsigned char U8; /* 0 to 255 */
typedef unsigned short U16; /* 0 to 65535 */
typedef signed char S8; /* -128 to 127 */
typedef signed short S16; /* -32768 to 32767 */
typedef float F32; /* IEEE Single Precision (S1E8M23) */
typedef double F64; /* IEEE Double Precision (S1E11M52) */
typedef unsigned long BOOL;
/*
* mainly for 64-bit linux, where long is 64 bits
* and win9x, where int is 16 bit.
*/
#if defined(vxworks)
typedef unsigned int V32; /* "void": enumerated or multiple fields */
typedef unsigned int U32; /* 0 to 4294967295 */
typedef signed int S32; /* -2147483648 to 2147483647 */
#else
typedef unsigned long V32; /* "void": enumerated or multiple fields */
typedef unsigned long U32; /* 0 to 4294967295 */
typedef signed long S32; /* -2147483648 to 2147483647 */
#endif
#ifndef TRUE
#define TRUE 1UL
#endif
#ifndef FALSE
#define FALSE 0UL
#endif
#endif
/****************************************************************************
* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
* *
* All Rights Reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
* *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
***************************************************************************/
#ifndef _XGI_TYPES_H_
#define _XGI_TYPES_H_
/****************************************************************************
* Typedefs *
***************************************************************************/
typedef unsigned char V8; /* "void": enumerated or multiple fields */
typedef unsigned short V16; /* "void": enumerated or multiple fields */
typedef unsigned char U8; /* 0 to 255 */
typedef unsigned short U16; /* 0 to 65535 */
typedef signed char S8; /* -128 to 127 */
typedef signed short S16; /* -32768 to 32767 */
typedef float F32; /* IEEE Single Precision (S1E8M23) */
typedef double F64; /* IEEE Double Precision (S1E11M52) */
typedef unsigned long BOOL;
/*
* mainly for 64-bit linux, where long is 64 bits
* and win9x, where int is 16 bit.
*/
#if defined(vxworks)
typedef unsigned int V32; /* "void": enumerated or multiple fields */
typedef unsigned int U32; /* 0 to 4294967295 */
typedef signed int S32; /* -2147483648 to 2147483647 */
#else
typedef unsigned long V32; /* "void": enumerated or multiple fields */
typedef unsigned long U32; /* 0 to 4294967295 */
typedef signed long S32; /* -2147483648 to 2147483647 */
#endif
#ifndef TRUE
#define TRUE 1UL
#endif
#ifndef FALSE
#define FALSE 0UL
#endif
#endif