Suspend/resume support (incomplete).
Jesse Barnes
parent
e918d2b781
commit
462d5a0dfc
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@ -70,6 +70,235 @@ static drm_bo_driver_t i915_bo_driver = {
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};
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#endif
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static int i915_suspend(struct pci_dev *pdev, pm_message_t state)
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{
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struct drm_device *dev = pci_get_drvdata(pdev);
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_output *output;
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int i;
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pci_save_state(pdev);
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/* Save video mode information for native mode-setting. */
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dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
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dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
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dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
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dev_priv->saveFPA0 = I915_READ(FPA0);
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dev_priv->saveFPA1 = I915_READ(FPA1);
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dev_priv->saveDPLL_A = I915_READ(DPLL_A);
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if (IS_I965G(dev))
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dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
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dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
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dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
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dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
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dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
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dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
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dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
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dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
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dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
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dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
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dev_priv->saveDSPABASE = I915_READ(DSPABASE);
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for(i= 0; i < 256; i++)
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dev_priv->savePaletteA[i] = I915_READ(PALETTE_A + (i << 2));
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if(dev->mode_config.num_crtc == 2) {
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dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
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dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
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dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
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dev_priv->saveFPB0 = I915_READ(FPB0);
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dev_priv->saveFPB1 = I915_READ(FPB1);
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dev_priv->saveDPLL_B = I915_READ(DPLL_B);
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if (IS_I965G(dev))
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dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
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dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
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dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
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dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
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dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
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dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
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dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
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dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
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dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
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dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
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dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
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for(i= 0; i < 256; i++)
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dev_priv->savePaletteB[i] =
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I915_READ(PALETTE_B + (i << 2));
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}
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if (IS_I965G(dev)) {
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dev_priv->saveDSPASURF = I915_READ(DSPASURF);
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dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
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}
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dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
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dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
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dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
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dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
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for(i = 0; i < 7; i++) {
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dev_priv->saveSWF[i] = I915_READ(SWF0 + (i << 2));
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dev_priv->saveSWF[i+7] = I915_READ(SWF00 + (i << 2));
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}
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dev_priv->saveSWF[14] = I915_READ(SWF30);
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dev_priv->saveSWF[15] = I915_READ(SWF31);
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dev_priv->saveSWF[16] = I915_READ(SWF32);
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if (IS_MOBILE(dev) && !IS_I830(dev))
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dev_priv->saveLVDS = I915_READ(LVDS);
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dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
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list_for_each_entry(output, &dev->mode_config.output_list, head)
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if (output->funcs->save)
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(*output->funcs->save) (output);
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#if 0 /* FIXME: save VGA bits */
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vgaHWUnlock(hwp);
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vgaHWSave(pScrn, vgaReg, VGA_SR_FONTS);
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#endif
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pci_disable_device(pdev);
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pci_set_power_state(pdev, PCI_D3hot);
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return 0;
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}
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static int i915_resume(struct pci_dev *pdev)
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{
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struct drm_device *dev = pci_get_drvdata(pdev);
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_output *output;
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struct drm_crtc *crtc;
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int i;
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pci_set_power_state(pdev, PCI_D0);
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pci_restore_state(pdev);
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pci_enable_device(pdev);
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/* Disable outputs */
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list_for_each_entry(output, &dev->mode_config.output_list, head)
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output->funcs->dpms(output, DPMSModeOff);
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i915_driver_wait_next_vblank(dev, 0);
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/* Disable pipes */
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
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crtc->funcs->dpms(crtc, DPMSModeOff);
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/* FIXME: wait for vblank on each pipe? */
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i915_driver_wait_next_vblank(dev, 0);
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if (IS_MOBILE(dev) && !IS_I830(dev))
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I915_WRITE(LVDS, dev_priv->saveLVDS);
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if (!IS_I830(dev) && !IS_845G(dev))
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I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
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if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
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I915_WRITE(DPLL_A, dev_priv->saveDPLL_A & ~DPLL_VCO_ENABLE);
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udelay(150);
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}
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I915_WRITE(FPA0, dev_priv->saveFPA0);
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I915_WRITE(FPA1, dev_priv->saveFPA1);
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I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
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udelay(150);
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if (IS_I965G(dev))
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I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
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else
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I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
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udelay(150);
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I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
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I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
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I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
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I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
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I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
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I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
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I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
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I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
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I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
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I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
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I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
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if (IS_I965G(dev))
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I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
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I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
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i915_driver_wait_next_vblank(dev, 0);
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I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
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I915_WRITE(DSPABASE, I915_READ(DSPABASE));
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i915_driver_wait_next_vblank(dev, 0);
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if(dev->mode_config.num_crtc == 2) {
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if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
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I915_WRITE(DPLL_B, dev_priv->saveDPLL_B & ~DPLL_VCO_ENABLE);
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udelay(150);
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}
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I915_WRITE(FPB0, dev_priv->saveFPB0);
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I915_WRITE(FPB1, dev_priv->saveFPB1);
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I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
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udelay(150);
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if (IS_I965G(dev))
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I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
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else
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I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
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udelay(150);
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I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
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I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
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I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
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I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
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I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
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I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
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I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
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I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
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I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
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I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
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I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
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if (IS_I965G(dev))
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I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
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I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
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i915_driver_wait_next_vblank(dev, 0);
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I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
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I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
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i915_driver_wait_next_vblank(dev, 0);
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}
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/* Restore outputs */
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list_for_each_entry(output, &dev->mode_config.output_list, head)
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if (output->funcs->restore)
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output->funcs->restore(output);
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I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
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I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
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I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
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I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
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for(i = 0; i < 256; i++)
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I915_WRITE(PALETTE_A + (i << 2), dev_priv->savePaletteA[i]);
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if(dev->mode_config.num_crtc == 2)
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for(i= 0; i < 256; i++)
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I915_WRITE(PALETTE_B + (i << 2), dev_priv->savePaletteB[i]);
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for(i = 0; i < 7; i++) {
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I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF[i]);
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I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF[i+7]);
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}
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I915_WRITE(SWF30, dev_priv->saveSWF[14]);
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I915_WRITE(SWF31, dev_priv->saveSWF[15]);
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I915_WRITE(SWF32, dev_priv->saveSWF[16]);
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#if 0 /* FIXME: restore VGA bits */
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vgaHWRestore(pScrn, vgaReg, VGA_SR_FONTS);
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vgaHWLock(hwp);
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#endif
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drm_initial_config(dev, 0);
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return 0;
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}
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static int probe(struct pci_dev *pdev, const struct pci_device_id *ent);
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static struct drm_driver driver = {
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/* don't use mtrr's here, the Xserver or user space app should
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@ -113,6 +342,8 @@ static struct drm_driver driver = {
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.id_table = pciidlist,
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.probe = probe,
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.remove = __devexit_p(drm_cleanup_pci),
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.suspend = i915_suspend,
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.resume = i915_resume,
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},
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#ifdef I915_HAVE_FENCE
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.fence_driver = &i915_fence_driver,
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@ -227,6 +227,7 @@ extern int i915_dma_cleanup(drm_device_t * dev);
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extern int i915_irq_emit(DRM_IOCTL_ARGS);
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extern int i915_irq_wait(DRM_IOCTL_ARGS);
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extern void i915_driver_wait_next_vblank(drm_device_t *dev, int pipe);
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extern int i915_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
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extern int i915_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence);
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extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
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@ -395,6 +396,39 @@ extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
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# define GPIO_DATA_VAL_IN (1 << 12)
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# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
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/* p317, 319
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*/
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#define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */
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#define VCLK2_VCO_N 0x600a
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#define VCLK2_VCO_DIV_SEL 0x6012
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#define VCLK_DIVISOR_VGA0 0x6000
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#define VCLK_DIVISOR_VGA1 0x6004
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#define VCLK_POST_DIV 0x6010
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/** Selects a post divisor of 4 instead of 2. */
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# define VGA1_PD_P2_DIV_4 (1 << 15)
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/** Overrides the p2 post divisor field */
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# define VGA1_PD_P1_DIV_2 (1 << 13)
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# define VGA1_PD_P1_SHIFT 8
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/** P1 value is 2 greater than this field */
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# define VGA1_PD_P1_MASK (0x1f << 8)
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/** Selects a post divisor of 4 instead of 2. */
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# define VGA0_PD_P2_DIV_4 (1 << 7)
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/** Overrides the p2 post divisor field */
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# define VGA0_PD_P1_DIV_2 (1 << 5)
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# define VGA0_PD_P1_SHIFT 0
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/** P1 value is 2 greater than this field */
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# define VGA0_PD_P1_MASK (0x1f << 0)
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#define POST_DIV_SELECT 0x70
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#define POST_DIV_1 0x00
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#define POST_DIV_2 0x10
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#define POST_DIV_4 0x20
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#define POST_DIV_8 0x30
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#define POST_DIV_16 0x40
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#define POST_DIV_32 0x50
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#define VCO_LOOP_DIV_BY_4M 0x00
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#define VCO_LOOP_DIV_BY_16M 0x04
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#define SRX_INDEX 0x3c4
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#define SRX_DATA 0x3c5
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@ -906,6 +940,58 @@ extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
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# define VGA_2X_MODE (1 << 30)
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# define VGA_PIPE_B_SELECT (1 << 29)
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/*
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* Some BIOS scratch area registers. The 845 (and 830?) store the amount
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* of video memory available to the BIOS in SWF1.
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*/
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#define SWF0 0x71410
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#define SWF1 0x71414
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#define SWF2 0x71418
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#define SWF3 0x7141c
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#define SWF4 0x71420
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#define SWF5 0x71424
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#define SWF6 0x71428
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/*
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* 855 scratch registers.
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*/
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#define SWF00 0x70410
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#define SWF01 0x70414
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#define SWF02 0x70418
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#define SWF03 0x7041c
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#define SWF04 0x70420
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#define SWF05 0x70424
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#define SWF06 0x70428
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#define SWF10 SWF0
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#define SWF11 SWF1
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#define SWF12 SWF2
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#define SWF13 SWF3
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#define SWF14 SWF4
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#define SWF15 SWF5
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#define SWF16 SWF6
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#define SWF30 0x72414
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#define SWF31 0x72418
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#define SWF32 0x7241c
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/*
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* Overlay registers. These are overlay registers accessed via MMIO.
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* Those loaded via the overlay register page are defined in i830_video.c.
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*/
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#define OVADD 0x30000
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#define DOVSTA 0x30008
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#define OC_BUF (0x3<<20)
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#define OGAMC5 0x30010
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#define OGAMC4 0x30014
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#define OGAMC3 0x30018
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#define OGAMC2 0x3001c
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#define OGAMC1 0x30020
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#define OGAMC0 0x30024
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/*
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* Palette registers
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*/
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@ -438,6 +438,19 @@ static int i915_driver_vblank_do_wait(drm_device_t *dev, unsigned int *sequence,
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return ret;
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}
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void i915_driver_wait_next_vblank(drm_device_t *dev, int pipe)
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{
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unsigned int seq;
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seq = pipe ? atomic_read(&dev->vbl_received2) + 1 :
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atomic_read(&dev->vbl_received) + 1;
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if (!pipe)
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i915_driver_vblank_do_wait(dev, &seq, &dev->vbl_received);
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else
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i915_driver_vblank_do_wait(dev, &seq, &dev->vbl_received2);
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}
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int i915_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence)
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{
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return i915_driver_vblank_do_wait(dev, sequence, &dev->vbl_received);
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