nouveau: rework nouveau_fifo_alloc() so the drm can create internal FIFOs
Ben Skeggs
parent
8d918b0b63
commit
4988fa4886
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@ -273,24 +273,21 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel)
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}
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#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV04_RAMFC_##offset, (val))
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static void nouveau_nv04_context_init(drm_device_t *dev,
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drm_nouveau_fifo_alloc_t *init)
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static void nouveau_nv04_context_init(drm_device_t *dev, int channel)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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struct nouveau_object *cb_obj;
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uint32_t fifoctx, ctx_size = 32;
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int i;
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cb_obj = dev_priv->fifos[init->channel].cmdbuf_obj;
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cb_obj = dev_priv->fifos[channel].cmdbuf_obj;
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fifoctx=NV_RAMIN+dev_priv->ramfc_offset+init->channel*ctx_size;
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fifoctx=NV_RAMIN+dev_priv->ramfc_offset+channel*ctx_size;
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// clear the fifo context
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for(i=0;i<ctx_size/4;i++)
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NV_WRITE(fifoctx+4*i,0x0);
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RAMFC_WR(DMA_PUT , init->put_base);
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RAMFC_WR(DMA_GET , init->put_base);
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RAMFC_WR(DMA_INSTANCE , nouveau_chip_instance_get(dev, cb_obj->instance));
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RAMFC_WR(DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES |
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@ -304,15 +301,14 @@ static void nouveau_nv04_context_init(drm_device_t *dev,
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#undef RAMFC_WR
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#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV10_RAMFC_##offset, (val))
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static void nouveau_nv10_context_init(drm_device_t *dev,
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drm_nouveau_fifo_alloc_t *init)
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static void nouveau_nv10_context_init(drm_device_t *dev, int channel)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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struct nouveau_object *cb_obj;
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uint32_t fifoctx;
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int i;
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cb_obj = dev_priv->fifos[init->channel].cmdbuf_obj;
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fifoctx = NV_RAMIN + dev_priv->ramfc_offset + init->channel*64;
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cb_obj = dev_priv->fifos[channel].cmdbuf_obj;
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fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64;
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for (i=0;i<64;i+=4)
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NV_WRITE(fifoctx + i, 0);
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@ -321,8 +317,6 @@ static void nouveau_nv10_context_init(drm_device_t *dev,
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* after channel's is put into DMA mode
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*/
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RAMFC_WR(DMA_PUT , init->put_base);
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RAMFC_WR(DMA_GET , init->put_base);
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RAMFC_WR(DMA_INSTANCE , nouveau_chip_instance_get(dev,
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cb_obj->instance));
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@ -335,25 +329,22 @@ static void nouveau_nv10_context_init(drm_device_t *dev,
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0x00000000);
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}
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static void nouveau_nv30_context_init(drm_device_t *dev,
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drm_nouveau_fifo_alloc_t *init)
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static void nouveau_nv30_context_init(drm_device_t *dev, int channel)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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struct nouveau_fifo *chan = &dev_priv->fifos[init->channel];
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struct nouveau_fifo *chan = &dev_priv->fifos[channel];
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struct nouveau_object *cb_obj;
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uint32_t fifoctx, grctx_inst, cb_inst, ctx_size = 64;
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int i;
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cb_obj = dev_priv->fifos[init->channel].cmdbuf_obj;
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cb_obj = dev_priv->fifos[channel].cmdbuf_obj;
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cb_inst = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance);
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grctx_inst = nouveau_chip_instance_get(dev, chan->ramin_grctx);
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fifoctx = NV_RAMIN + dev_priv->ramfc_offset + init->channel * ctx_size;
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fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel * ctx_size;
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for (i = 0; i < ctx_size; i += 4)
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NV_WRITE(fifoctx + i, 0);
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RAMFC_WR(DMA_PUT, init->put_base);
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RAMFC_WR(DMA_GET, init->put_base);
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RAMFC_WR(REF_CNT, NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
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RAMFC_WR(DMA_INSTANCE, cb_inst);
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RAMFC_WR(DMA_STATE, NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
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@ -371,8 +362,6 @@ static void nouveau_nv30_context_init(drm_device_t *dev,
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RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP));
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RAMFC_WR(ACQUIRE_TIMEOUT, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
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RAMFC_WR(SEMAPHORE, NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
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RAMFC_WR(DMA_SUBROUTINE, init->put_base);
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}
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static void nouveau_nv10_context_save(drm_device_t *dev)
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@ -401,25 +390,22 @@ static void nouveau_nv10_context_save(drm_device_t *dev)
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#undef RAMFC_WR
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#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV40_RAMFC_##offset, (val))
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static void nouveau_nv40_context_init(drm_device_t *dev,
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drm_nouveau_fifo_alloc_t *init)
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static void nouveau_nv40_context_init(drm_device_t *dev, int channel)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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struct nouveau_fifo *chan = &dev_priv->fifos[init->channel];
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struct nouveau_fifo *chan = &dev_priv->fifos[channel];
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uint32_t fifoctx, cb_inst, grctx_inst;
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int i;
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cb_inst = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance);
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grctx_inst = nouveau_chip_instance_get(dev, chan->ramin_grctx);
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fifoctx = NV_RAMIN + dev_priv->ramfc_offset + init->channel*128;
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fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*128;
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for (i=0;i<128;i+=4)
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NV_WRITE(fifoctx + i, 0);
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/* Fill entries that are seen filled in dumps of nvidia driver just
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* after channel's is put into DMA mode
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*/
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RAMFC_WR(DMA_PUT , init->put_base);
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RAMFC_WR(DMA_GET , init->put_base);
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RAMFC_WR(DMA_INSTANCE , cb_inst);
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RAMFC_WR(DMA_FETCH , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
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NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
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@ -428,7 +414,6 @@ static void nouveau_nv40_context_init(drm_device_t *dev,
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NV_PFIFO_CACHE1_BIG_ENDIAN |
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#endif
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0x30000000 /* no idea.. */);
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RAMFC_WR(DMA_SUBROUTINE, init->put_base);
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RAMFC_WR(GRCTX_INSTANCE, grctx_inst);
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RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF);
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}
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@ -503,12 +488,12 @@ nouveau_fifo_context_restore(drm_device_t *dev, int channel)
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}
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/* allocates and initializes a fifo for user space consumption */
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static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init, DRMFILE filp)
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static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp)
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{
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int i;
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int ret;
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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struct nouveau_object *cb_obj;
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int channel;
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/*
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* Alright, here is the full story
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@ -518,31 +503,29 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init,
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* (woo, full userspace command submission !)
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* When there are no more contexts, you lost
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*/
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for(i=0;i<nouveau_fifo_number(dev);i++)
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if (dev_priv->fifos[i].used==0)
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for(channel=0; channel<nouveau_fifo_number(dev); channel++)
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if (dev_priv->fifos[channel].used==0)
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break;
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DRM_INFO("Allocating FIFO number %d\n", i);
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/* no more fifos. you lost. */
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if (i==nouveau_fifo_number(dev))
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if (channel==nouveau_fifo_number(dev))
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return DRM_ERR(EINVAL);
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(*chan_ret) = channel;
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DRM_INFO("Allocating FIFO number %d\n", channel);
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/* that fifo is used */
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dev_priv->fifos[i].used = 1;
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dev_priv->fifos[i].filp = filp;
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dev_priv->fifos[channel].used = 1;
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dev_priv->fifos[channel].filp = filp;
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/* FIFO has no objects yet */
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dev_priv->fifos[i].objs = NULL;
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dev_priv->fifos[channel].objs = NULL;
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/* allocate a command buffer, and create a dma object for the gpu */
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ret = nouveau_fifo_cmdbuf_alloc(dev, i);
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ret = nouveau_fifo_cmdbuf_alloc(dev, channel);
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if (ret) {
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nouveau_fifo_free(dev, i);
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nouveau_fifo_free(dev, channel);
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return ret;
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}
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cb_obj = dev_priv->fifos[i].cmdbuf_obj;
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init->channel = i;
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init->put_base = 0;
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cb_obj = dev_priv->fifos[channel].cmdbuf_obj;
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nouveau_wait_for_idle(dev);
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@ -557,58 +540,58 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init,
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{
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case NV_04:
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case NV_05:
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nv04_graph_context_create(dev, init->channel);
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nouveau_nv04_context_init(dev, init);
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nv04_graph_context_create(dev, channel);
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nouveau_nv04_context_init(dev, channel);
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break;
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case NV_10:
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nv10_graph_context_create(dev, init->channel);
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nouveau_nv10_context_init(dev, init);
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nv10_graph_context_create(dev, channel);
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nouveau_nv10_context_init(dev, channel);
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break;
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case NV_20:
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ret = nv20_graph_context_create(dev, init->channel);
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ret = nv20_graph_context_create(dev, channel);
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if (ret) {
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nouveau_fifo_free(dev, init->channel);
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nouveau_fifo_free(dev, channel);
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return ret;
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}
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nouveau_nv10_context_init(dev, init);
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nouveau_nv10_context_init(dev, channel);
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break;
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case NV_30:
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ret = nv30_graph_context_create(dev, init->channel);
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ret = nv30_graph_context_create(dev, channel);
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if (ret) {
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nouveau_fifo_free(dev, init->channel);
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nouveau_fifo_free(dev, channel);
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return ret;
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}
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nouveau_nv30_context_init(dev, init);
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nouveau_nv30_context_init(dev, channel);
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break;
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case NV_40:
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case NV_44:
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case NV_50:
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ret = nv40_graph_context_create(dev, init->channel);
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ret = nv40_graph_context_create(dev, channel);
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if (ret) {
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nouveau_fifo_free(dev, init->channel);
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nouveau_fifo_free(dev, channel);
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return ret;
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}
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nouveau_nv40_context_init(dev, init);
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nouveau_nv40_context_init(dev, channel);
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break;
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}
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/* enable the fifo dma operation */
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NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<init->channel));
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NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<channel));
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/* setup channel's default get/put values */
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NV_WRITE(NV03_FIFO_REGS_DMAPUT(init->channel), init->put_base);
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NV_WRITE(NV03_FIFO_REGS_DMAGET(init->channel), init->put_base);
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NV_WRITE(NV03_FIFO_REGS_DMAPUT(channel), 0);
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NV_WRITE(NV03_FIFO_REGS_DMAGET(channel), 0);
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/* If this is the first channel, setup PFIFO ourselves. For any
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* other case, the GPU will handle this when it switches contexts.
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*/
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if (dev_priv->fifo_alloc_count == 0) {
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nouveau_fifo_context_restore(dev, init->channel);
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nouveau_fifo_context_restore(dev, channel);
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if (dev_priv->card_type >= NV_30) {
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struct nouveau_fifo *chan;
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uint32_t inst;
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chan = &dev_priv->fifos[init->channel];
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chan = &dev_priv->fifos[channel];
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inst = nouveau_chip_instance_get(dev,
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chan->ramin_grctx);
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@ -629,22 +612,9 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init,
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/* reenable the fifo caches */
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NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
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/* make the fifo available to user space */
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/* first, the fifo control regs */
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init->ctrl = dev_priv->mmio->offset + NV03_FIFO_REGS(init->channel);
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init->ctrl_size = NV03_FIFO_REGS_SIZE;
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ret = drm_addmap(dev, init->ctrl, init->ctrl_size, _DRM_REGISTERS,
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0, &dev_priv->fifos[init->channel].regs);
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if (ret != 0)
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return ret;
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/* pass back FIFO map info to the caller */
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init->cmdbuf = dev_priv->fifos[init->channel].cmdbuf_mem->start;
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init->cmdbuf_size = dev_priv->fifos[init->channel].cmdbuf_mem->size;
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dev_priv->fifo_alloc_count++;
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DRM_INFO("%s: initialised FIFO %d\n", __func__, init->channel);
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DRM_INFO("%s: initialised FIFO %d\n", __func__, channel);
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return 0;
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}
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@ -729,15 +699,36 @@ nouveau_fifo_owner(drm_device_t *dev, DRMFILE filp, int channel)
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static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS)
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{
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DRM_DEVICE;
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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drm_nouveau_fifo_alloc_t init;
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int res;
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DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_fifo_alloc_t __user *) data, sizeof(init));
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res=nouveau_fifo_alloc(dev,&init,filp);
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if (!res)
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DRM_COPY_TO_USER_IOCTL((drm_nouveau_fifo_alloc_t __user *)data, init, sizeof(init));
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DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_fifo_alloc_t __user *) data,
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sizeof(init));
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return res;
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res = nouveau_fifo_alloc(dev, &init.channel, filp);
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if (res)
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return res;
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/* this should probably disappear in the next abi break? */
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init.put_base = 0;
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/* make the fifo available to user space */
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/* first, the fifo control regs */
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init.ctrl = dev_priv->mmio->offset + NV03_FIFO_REGS(init.channel);
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init.ctrl_size = NV03_FIFO_REGS_SIZE;
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res = drm_addmap(dev, init.ctrl, init.ctrl_size, _DRM_REGISTERS,
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0, &dev_priv->fifos[init.channel].regs);
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if (res != 0)
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return res;
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/* pass back FIFO map info to the caller */
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init.cmdbuf = dev_priv->fifos[init.channel].cmdbuf_mem->start;
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init.cmdbuf_size = dev_priv->fifos[init.channel].cmdbuf_mem->size;
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DRM_COPY_TO_USER_IOCTL((drm_nouveau_fifo_alloc_t __user *)data,
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init, sizeof(init));
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return 0;
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}
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/***********************************
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