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NV40: *Now* fifo ctx switching works for me.. 

Ok, I lied before.. it was a fluke it worked and required magic to repeat it..
It actually helps to fill in RAMFC entries in the correct place.

The code also clears RAMIN entirely instead of just the hash-table.
main
Ben Skeggs 2006-10-17 12:33:49 +11:00
parent 98e718d48f
commit 4b43ee63f9
2 changed files with 7 additions and 6 deletions
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7
shared-core/nouveau_fifo.c
View File

@ -92,12 +92,15 @@ static void nouveau_fifo_init(drm_device_t* dev)
((dev_priv->objs.ht_bits - 9) << 16) |
(dev_priv->objs.ht_base >> 8)
);
dev_priv->ramfc_offset=0x12000;
dev_priv->ramro_offset=0x11200;
/* RAMFC needs to be at RAMIN+0x20000 on NV40, I currently don't know
* how to move it..
*/
dev_priv->ramfc_offset=0x20000;
if (dev_priv->card_type < NV_40)
NV_WRITE(NV_PFIFO_RAMFC, dev_priv->ramfc_offset>>8); /* RAMIN+0x11000 0.5k */
else
NV_WRITE(0x2220, 0x30002);
dev_priv->ramro_offset=0x11200;
NV_WRITE(NV_PFIFO_RAMRO, dev_priv->ramro_offset>>8); /* RAMIN+0x11200 0.5k */
NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001);
NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000);

6
shared-core/nouveau_object.c
View File

@ -303,10 +303,8 @@ void nouveau_hash_table_init(drm_device_t* dev)
dev_priv->objs.inst_bmap = drm_calloc
(1, dev_priv->objs.num_instance/32, DRM_MEM_DRIVER);
/* clear the hash table */
ht_start = NV_RAMIN+dev_priv->objs.ht_base;
ht_end = ht_start + dev_priv->objs.ht_size;
for (i=ht_start; i<ht_end; i+=4)
/* clear all of RAMIN */
for (i=0x00700000; i<0x00800000; i+=4)
NV_WRITE(i, 0x00000000);
}