radeon: do proper memory controller init and setup
Dave Airlie
parent
b6c1a2f7ee
commit
515aa0800c
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@ -707,6 +707,176 @@ int radeon_alloc_gart_objects(struct drm_device *dev)
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}
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static bool avivo_get_mc_idle(struct drm_device *dev)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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if (dev_priv->chip_family >= CHIP_R600) {
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/* no idea where this is on r600 yet */
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return true;
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} else if (dev_priv->chip_family == CHIP_RV515) {
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if (radeon_read_mc_reg(dev_priv, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE)
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return true;
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else
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return false;
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} else if (dev_priv->chip_family == CHIP_RS600) {
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if (radeon_read_mc_reg(dev_priv, RS600_MC_STATUS) & RS600_MC_STATUS_IDLE)
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return true;
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else
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return false;
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} else if ((dev_priv->chip_family == CHIP_RS690) ||
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(dev_priv->chip_family == CHIP_RS740)) {
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if (radeon_read_mc_reg(dev_priv, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE)
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return true;
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else
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return false;
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} else {
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if (radeon_read_mc_reg(dev_priv, R520_MC_STATUS) & R520_MC_STATUS_IDLE)
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return true;
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else
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return false;
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}
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}
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static void avivo_disable_mc_clients(struct drm_device *dev)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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uint32_t tmp;
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int timeout;
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radeon_do_wait_for_idle(dev_priv);
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RADEON_WRITE(AVIVO_D1VGA_CONTROL, RADEON_READ(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
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RADEON_WRITE(AVIVO_D2VGA_CONTROL, RADEON_READ(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
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tmp = RADEON_READ(AVIVO_D1CRTC_CONTROL);
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RADEON_WRITE(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
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tmp = RADEON_READ(AVIVO_D2CRTC_CONTROL);
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RADEON_WRITE(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
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tmp = RADEON_READ(AVIVO_D2CRTC_CONTROL);
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udelay(1000);
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timeout = 0;
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while (!(avivo_get_mc_idle(dev))) {
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if (++timeout > 100000) {
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DRM_ERROR("Timeout waiting for memory controller to update settings\n");
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DRM_ERROR("Bad things may or may not happen\n");
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}
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udelay(10);
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}
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}
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static inline u32 radeon_busy_wait(struct drm_device *dev, uint32_t reg, uint32_t bits,
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unsigned int timeout)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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u32 status;
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do {
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udelay(10);
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status = RADEON_READ(reg);
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timeout--;
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} while(status != 0xffffffff && (status & bits) && (timeout > 0));
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if (timeout == 0)
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status = 0xffffffff;
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return status;
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}
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/* Wait for vertical sync on primary CRTC */
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static void radeon_wait_for_vsync(struct drm_device *dev)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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uint32_t crtc_gen_cntl;
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int ret;
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crtc_gen_cntl = RADEON_READ(RADEON_CRTC_GEN_CNTL);
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if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
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!(crtc_gen_cntl & RADEON_CRTC_EN))
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return;
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/* Clear the CRTC_VBLANK_SAVE bit */
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RADEON_WRITE(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
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radeon_busy_wait(dev, RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE, 2000);
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}
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/* Wait for vertical sync on primary CRTC */
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static void radeon_wait_for_vsync2(struct drm_device *dev)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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uint32_t crtc2_gen_cntl;
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struct timeval timeout;
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crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);
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if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
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!(crtc2_gen_cntl & RADEON_CRTC2_EN))
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return;
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/* Clear the CRTC_VBLANK_SAVE bit */
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RADEON_WRITE(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
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radeon_busy_wait(dev, RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE, 2000);
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}
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static void legacy_disable_mc_clients(struct drm_device *dev)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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uint32_t old_mc_status, status_idle;
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uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;
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uint32_t status;
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radeon_do_wait_for_idle(dev_priv);
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if (dev_priv->flags & RADEON_IS_IGP)
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return;
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old_mc_status = RADEON_READ(RADEON_MC_STATUS);
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/* stop display and memory access */
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ov0_scale_cntl = RADEON_READ(RADEON_OV0_SCALE_CNTL);
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RADEON_WRITE(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
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crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
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RADEON_WRITE(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
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crtc_gen_cntl = RADEON_READ(RADEON_CRTC_GEN_CNTL);
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radeon_wait_for_vsync(dev);
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RADEON_WRITE(RADEON_CRTC_GEN_CNTL,
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(crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) |
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RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
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if (!(dev_priv->flags & RADEON_SINGLE_CRTC)) {
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crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);
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radeon_wait_for_vsync2(dev);
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RADEON_WRITE(RADEON_CRTC2_GEN_CNTL,
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(crtc2_gen_cntl &
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~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) |
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RADEON_CRTC2_DISP_REQ_EN_B);
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}
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udelay(500);
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if (radeon_is_r300(dev_priv))
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status_idle = R300_MC_IDLE;
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else
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status_idle = RADEON_MC_IDLE;
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status = radeon_busy_wait(dev, RADEON_MC_STATUS, status_idle, 200000);
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if (status == 0xffffffff) {
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DRM_ERROR("Timeout waiting for memory controller to update settings\n");
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DRM_ERROR("Bad things may or may not happen\n");
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}
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}
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void radeon_init_memory_map(struct drm_device *dev)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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@ -776,6 +946,14 @@ void radeon_init_memory_map(struct drm_device *dev)
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else
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dev_priv->fb_location = (dev_priv->mc_fb_location & 0xffff) << 16;
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/* updating mc regs here */
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if (radeon_is_avivo(dev_priv))
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avivo_disable_mc_clients(dev);
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else
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legacy_disable_mc_clients(dev);
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radeon_write_fb_location(dev_priv, dev_priv->mc_fb_location);
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if (radeon_is_avivo(dev_priv)) {
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if (dev_priv->chip_family >= CHIP_R600)
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RADEON_WRITE(R600_HDP_NONSURFACE_BASE, (dev_priv->mc_fb_location << 16) & 0xff0000);
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@ -783,8 +961,6 @@ void radeon_init_memory_map(struct drm_device *dev)
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RADEON_WRITE(AVIVO_HDP_FB_LOCATION, dev_priv->mc_fb_location);
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}
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radeon_write_fb_location(dev_priv, dev_priv->mc_fb_location);
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dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
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dev_priv->fb_size =
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((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
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@ -356,7 +356,7 @@ static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
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return -EBUSY;
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}
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static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
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int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
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{
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int i, ret;
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@ -491,6 +491,7 @@ extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
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extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
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extern int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv);
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extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
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extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
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