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Add support for GL_ATI_fragment_shader, new packets R200_EMIT_PP_AFS_0/1, 

R200_EMIT_PP_TXCTLALL_0-5 (replaces R200_EMIT_PP_TXFILTER_0-5, 2 more
    regs) and R200_EMIT_ATF_TFACTOR (replaces R200_EMIT_TFACTOR_0 (8 consts
    instead of 6)
main
Roland Scheidegger 2005-09-09 22:35:49 +00:00
parent c8b5a9f8cc
commit 53c8037786
3 changed files with 37 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
shared-core/radeon_drm.h
View File

@ -152,7 +152,16 @@
#define RADEON_EMIT_PP_CUBIC_FACES_2 82 #define RADEON_EMIT_PP_CUBIC_FACES_2 82
#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
#define R200_EMIT_PP_TRI_PERF_CNTL 84 #define R200_EMIT_PP_TRI_PERF_CNTL 84
#define RADEON_MAX_STATE_PACKETS 85 #define R200_EMIT_PP_AFS_0 85
#define R200_EMIT_PP_AFS_1 86
#define R200_EMIT_ATF_TFACTOR 87
#define R200_EMIT_PP_TXCTLALL_0 88
#define R200_EMIT_PP_TXCTLALL_1 89
#define R200_EMIT_PP_TXCTLALL_2 90
#define R200_EMIT_PP_TXCTLALL_3 91
#define R200_EMIT_PP_TXCTLALL_4 92
#define R200_EMIT_PP_TXCTLALL_5 93
#define RADEON_MAX_STATE_PACKETS 94
/* Commands understood by cmd_buffer ioctl. More can be added but /* Commands understood by cmd_buffer ioctl. More can be added but
* obviously these can't be removed or changed: * obviously these can't be removed or changed:

10
shared-core/radeon_drv.h
View File

@ -38,7 +38,7 @@
#define DRIVER_NAME "radeon" #define DRIVER_NAME "radeon"
#define DRIVER_DESC "ATI Radeon" #define DRIVER_DESC "ATI Radeon"
#define DRIVER_DATE "20050720" #define DRIVER_DATE "20050905"
/* Interface history: /* Interface history:
* *
@ -83,10 +83,13 @@
* 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
* texture filtering on r200 * texture filtering on r200
* 1.17- Add initial support for R300 (3D). * 1.17- Add initial support for R300 (3D).
* 1.18- Add support for GL_ATI_fragment_shader, new packets R200_EMIT_PP_AFS_0/1,
R200_EMIT_PP_TXCTLALL_0-5 (replaces R200_EMIT_PP_TXFILTER_0-5, 2 more regs)
and R200_EMIT_ATF_TFACTOR (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
*/ */
#define DRIVER_MAJOR 1 #define DRIVER_MAJOR 1
#define DRIVER_MINOR 17 #define DRIVER_MINOR 18
#define DRIVER_PATCHLEVEL 0 #define DRIVER_PATCHLEVEL 0
enum radeon_family { enum radeon_family {
@ -870,6 +873,9 @@ extern int r300_do_cp_cmdbuf( drm_device_t* dev,
#define R200_PP_TRI_PERF 0x2cf8 #define R200_PP_TRI_PERF 0x2cf8
#define R200_PP_AFS_0 0x2f80
#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
/* MPEG settings from VHA code */ /* MPEG settings from VHA code */
#define RADEON_VHA_SETTO16_1 0x2694 #define RADEON_VHA_SETTO16_1 0x2694
#define RADEON_VHA_SETTO16_2 0x2680 #define RADEON_VHA_SETTO16_2 0x2680

20
shared-core/radeon_state.c
View File

@ -210,6 +210,15 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
case RADEON_EMIT_PP_CUBIC_FACES_1: case RADEON_EMIT_PP_CUBIC_FACES_1:
case RADEON_EMIT_PP_CUBIC_FACES_2: case RADEON_EMIT_PP_CUBIC_FACES_2:
case R200_EMIT_PP_TRI_PERF_CNTL: case R200_EMIT_PP_TRI_PERF_CNTL:
case R200_EMIT_PP_AFS_0:
case R200_EMIT_PP_AFS_1:
case R200_EMIT_ATF_TFACTOR:
case R200_EMIT_PP_TXCTLALL_0:
case R200_EMIT_PP_TXCTLALL_1:
case R200_EMIT_PP_TXCTLALL_2:
case R200_EMIT_PP_TXCTLALL_3:
case R200_EMIT_PP_TXCTLALL_4:
case R200_EMIT_PP_TXCTLALL_5:
/* These packets don't contain memory offsets */ /* These packets don't contain memory offsets */
break; break;
@ -583,7 +592,16 @@ static struct {
RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, {
RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, {
RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, {
R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, {
R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, { /* 85 */
R200_PP_AFS_1, 32, "R200_PP_AFS_1"}, {
R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, {
R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, {
R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, {
R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, {
R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, {
R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, {
R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
}; };
/* ================================================================ /* ================================================================