amdgpu: use common fence structure for dependencies as well.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
main
Christian König 2015-07-09 11:48:32 +02:00 committed by Alex Deucher
parent f91b56dc8c
commit 5463d2e83a
5 changed files with 17 additions and 40 deletions

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@ -57,7 +57,7 @@ struct drm_amdgpu_info_hw_ip;
#define AMDGPU_TIMEOUT_INFINITE 0xffffffffffffffffull #define AMDGPU_TIMEOUT_INFINITE 0xffffffffffffffffull
/** /**
* Used in amdgpu_cs_query_fence::flags, meaning that the given timeout * Used in amdgpu_cs_query_fence_status(), meaning that the given timeout
* is absolute. * is absolute.
*/ */
#define AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE (1 << 0) #define AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE (1 << 0)
@ -266,13 +266,14 @@ struct amdgpu_gds_resource_info {
}; };
/** /**
* Structure describing CS dependency * Structure describing CS fence
* *
* \sa amdgpu_cs_request, amdgpu_cs_submit() * \sa amdgpu_cs_query_fence_status(), amdgpu_cs_request, amdgpu_cs_submit()
* *
*/ */
struct amdgpu_cs_dep_info { struct amdgpu_cs_fence {
/** Context to which the fence belongs */
/** In which context IB was sent to execution */
amdgpu_context_handle context; amdgpu_context_handle context;
/** To which HW IP type the fence belongs */ /** To which HW IP type the fence belongs */
@ -347,7 +348,7 @@ struct amdgpu_cs_request {
* Array of dependencies which need to be met before * Array of dependencies which need to be met before
* execution can start. * execution can start.
*/ */
struct amdgpu_cs_dep_info *dependencies; struct amdgpu_cs_fence *dependencies;
/** Number of IBs to submit in the field ibs. */ /** Number of IBs to submit in the field ibs. */
uint32_t number_of_ibs; uint32_t number_of_ibs;
@ -358,30 +359,6 @@ struct amdgpu_cs_request {
struct amdgpu_cs_ib_info *ibs; struct amdgpu_cs_ib_info *ibs;
}; };
/**
* Structure describing request to check submission state using fence
*
* \sa amdgpu_cs_query_fence_status()
*
*/
struct amdgpu_cs_query_fence {
/** In which context IB was sent to execution */
amdgpu_context_handle context;
/** To which HW IP type the fence belongs */
unsigned ip_type;
/** IP instance index if there are several IPs of the same type. */
unsigned ip_instance;
/** Ring index of the HW IP */
uint32_t ring;
/** Specify fence for which we need to check submission status.*/
uint64_t fence;
};
/** /**
* Structure which provide information about GPU VM MC Address space * Structure which provide information about GPU VM MC Address space
* alignments requirements * alignments requirements
@ -919,7 +896,7 @@ int amdgpu_cs_submit(amdgpu_context_handle context,
* *
* \sa amdgpu_cs_submit() * \sa amdgpu_cs_submit()
*/ */
int amdgpu_cs_query_fence_status(struct amdgpu_cs_query_fence *fence, int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
uint64_t timeout_ns, uint64_t timeout_ns,
uint64_t flags, uint64_t flags,
uint32_t *expired); uint32_t *expired);

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@ -259,7 +259,7 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context,
} }
for (i = 0; i < ibs_request->number_of_dependencies; ++i) { for (i = 0; i < ibs_request->number_of_dependencies; ++i) {
struct amdgpu_cs_dep_info *info = &ibs_request->dependencies[i]; struct amdgpu_cs_fence *info = &ibs_request->dependencies[i];
struct drm_amdgpu_cs_chunk_dep *dep = &dependencies[i]; struct drm_amdgpu_cs_chunk_dep *dep = &dependencies[i];
dep->ip_type = info->ip_type; dep->ip_type = info->ip_type;
dep->ip_instance = info->ip_instance; dep->ip_instance = info->ip_instance;
@ -379,7 +379,7 @@ static int amdgpu_ioctl_wait_cs(amdgpu_context_handle context,
return 0; return 0;
} }
int amdgpu_cs_query_fence_status(struct amdgpu_cs_query_fence *fence, int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
uint64_t timeout_ns, uint64_t timeout_ns,
uint64_t flags, uint64_t flags,
uint32_t *expired) uint32_t *expired)

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@ -161,7 +161,7 @@ static void amdgpu_command_submission_gfx_separate_ibs(void)
uint64_t ib_result_mc_address, ib_result_ce_mc_address; uint64_t ib_result_mc_address, ib_result_ce_mc_address;
struct amdgpu_cs_request ibs_request = {0}; struct amdgpu_cs_request ibs_request = {0};
struct amdgpu_cs_ib_info ib_info[2]; struct amdgpu_cs_ib_info ib_info[2];
struct amdgpu_cs_query_fence fence_status = {0}; struct amdgpu_cs_fence fence_status = {0};
uint32_t *ptr; uint32_t *ptr;
uint32_t expired; uint32_t expired;
amdgpu_bo_list_handle bo_list; amdgpu_bo_list_handle bo_list;
@ -243,7 +243,7 @@ static void amdgpu_command_submission_gfx_shared_ib(void)
uint64_t ib_result_mc_address; uint64_t ib_result_mc_address;
struct amdgpu_cs_request ibs_request = {0}; struct amdgpu_cs_request ibs_request = {0};
struct amdgpu_cs_ib_info ib_info[2]; struct amdgpu_cs_ib_info ib_info[2];
struct amdgpu_cs_query_fence fence_status = {0}; struct amdgpu_cs_fence fence_status = {0};
uint32_t *ptr; uint32_t *ptr;
uint32_t expired; uint32_t expired;
amdgpu_bo_list_handle bo_list; amdgpu_bo_list_handle bo_list;
@ -323,7 +323,7 @@ static void amdgpu_command_submission_compute(void)
uint64_t ib_result_mc_address; uint64_t ib_result_mc_address;
struct amdgpu_cs_request ibs_request; struct amdgpu_cs_request ibs_request;
struct amdgpu_cs_ib_info ib_info; struct amdgpu_cs_ib_info ib_info;
struct amdgpu_cs_query_fence fence_status; struct amdgpu_cs_fence fence_status;
uint32_t *ptr; uint32_t *ptr;
uint32_t expired; uint32_t expired;
int i, r, instance; int i, r, instance;
@ -358,7 +358,7 @@ static void amdgpu_command_submission_compute(void)
ibs_request.ibs = &ib_info; ibs_request.ibs = &ib_info;
ibs_request.resources = bo_list; ibs_request.resources = bo_list;
memset(&fence_status, 0, sizeof(struct amdgpu_cs_query_fence)); memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
r = amdgpu_cs_submit(context_handle, 0, r = amdgpu_cs_submit(context_handle, 0,
&ibs_request, 1, &fence_status.fence); &ibs_request, 1, &fence_status.fence);
CU_ASSERT_EQUAL(r, 0); CU_ASSERT_EQUAL(r, 0);
@ -400,7 +400,7 @@ static void amdgpu_sdma_test_exec_cs(amdgpu_context_handle context_handle,
amdgpu_bo_handle ib_result_handle; amdgpu_bo_handle ib_result_handle;
void *ib_result_cpu; void *ib_result_cpu;
uint64_t ib_result_mc_address; uint64_t ib_result_mc_address;
struct amdgpu_cs_query_fence fence_status = {0}; struct amdgpu_cs_fence fence_status = {0};
amdgpu_bo_handle *all_res = alloca(sizeof(resources[0]) * (res_cnt + 1)); amdgpu_bo_handle *all_res = alloca(sizeof(resources[0]) * (res_cnt + 1));
/* prepare CS */ /* prepare CS */

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@ -113,7 +113,7 @@ static int submit(unsigned ndw, unsigned ip)
{ {
struct amdgpu_cs_request ibs_request = {0}; struct amdgpu_cs_request ibs_request = {0};
struct amdgpu_cs_ib_info ib_info = {0}; struct amdgpu_cs_ib_info ib_info = {0};
struct amdgpu_cs_query_fence fence_status = {0}; struct amdgpu_cs_fence fence_status = {0};
uint32_t expired; uint32_t expired;
int r; int r;

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@ -130,7 +130,7 @@ static int submit(unsigned ndw, unsigned ip)
{ {
struct amdgpu_cs_request ibs_request = {0}; struct amdgpu_cs_request ibs_request = {0};
struct amdgpu_cs_ib_info ib_info = {0}; struct amdgpu_cs_ib_info ib_info = {0};
struct amdgpu_cs_query_fence fence_status = {0}; struct amdgpu_cs_fence fence_status = {0};
uint32_t expired; uint32_t expired;
int r; int r;