amdgpu: cleanup public interface style
Fix some style problems, adjust to a common indentation, reorder two function definitions and remove stale comments. No intended functional change. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>main
Christian König
Alex Deucher
parent
4a9f5f2e1e
commit
558e1294f2
164
amdgpu/amdgpu.h
164
amdgpu/amdgpu.h
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@ -232,7 +232,6 @@ struct amdgpu_bo_import_result {
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uint64_t virtual_mc_base_address;
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};
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/**
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*
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* Structure to describe GDS partitioning information.
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@ -270,8 +269,7 @@ struct amdgpu_cs_dep_info {
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/** Ring index of the HW IP */
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uint32_t ring;
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/** Specify fence for which we need to check
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* submission status.*/
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/** Specify fence for which we need to check submission status.*/
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uint64_t fence;
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};
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@ -291,7 +289,6 @@ struct amdgpu_cs_ib_info {
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/**
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* Size of Command Buffer to be submitted.
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* - The size is in units of dwords (4 bytes).
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* - Must be less or equal to the size of allocated IB
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* - Could be 0
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*/
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uint32_t size;
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@ -372,8 +369,7 @@ struct amdgpu_cs_query_fence {
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/** Flags */
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uint64_t flags;
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/** Specify fence for which we need to check
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* submission status.*/
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/** Specify fence for which we need to check submission status.*/
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uint64_t fence;
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};
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@ -394,7 +390,6 @@ struct amdgpu_buffer_size_alignments {
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uint64_t size_remote;
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};
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/**
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* Structure which provide information about heap
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*
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@ -420,8 +415,6 @@ struct amdgpu_heap_info {
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uint64_t max_allocation;
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};
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/**
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* Describe GPU h/w info needed for UMD correct initialization
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*
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@ -430,7 +423,7 @@ struct amdgpu_heap_info {
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struct amdgpu_gpu_info {
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/** Asic id */
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uint32_t asic_id;
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/**< Chip revision */
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/** Chip revision */
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uint32_t chip_rev;
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/** Chip external revision */
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uint32_t chip_external_rev;
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@ -496,14 +489,14 @@ struct amdgpu_gpu_info {
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*
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*/
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/**
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*
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* \param fd - \c [in] File descriptor for AMD GPU device
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* received previously as the result of
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* e.g. drmOpen() call.
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* For legacy fd type, the DRI2/DRI3 authentication
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* should be done before calling this function.
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* For legacy fd type, the DRI2/DRI3
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* authentication should be done before
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* calling this function.
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* \param major_version - \c [out] Major version of library. It is assumed
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* that adding new functionality will cause
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* increase in major version
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@ -525,8 +518,6 @@ int amdgpu_device_initialize(int fd,
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uint32_t *minor_version,
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amdgpu_device_handle *device_handle);
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/**
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*
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* When access to such library does not needed any more the special
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@ -547,7 +538,6 @@ int amdgpu_device_initialize(int fd,
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*/
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int amdgpu_device_deinitialize(amdgpu_device_handle device_handle);
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/*
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* Memory Management
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*
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@ -651,6 +641,42 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
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uint32_t shared_handle,
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struct amdgpu_bo_import_result *output);
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/**
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* Request GPU access to user allocated memory e.g. via "malloc"
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*
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* \param dev - [in] Device handle. See #amdgpu_device_initialize()
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* \param cpu - [in] CPU address of user allocated memory which we
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* want to map to GPU address space (make GPU accessible)
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* (This address must be correctly aligned).
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* \param size - [in] Size of allocation (must be correctly aligned)
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* \param amdgpu_bo_alloc_result - [out] Handle of allocation to be passed as
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* resource on submission and be used in other operations.
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*
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*
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* \return 0 on success
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* >0 - AMD specific error code
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* <0 - Negative POSIX Error code
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*
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* \note
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* This call doesn't guarantee that such memory will be persistently
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* "locked" / make non-pageable. The purpose of this call is to provide
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* opportunity for GPU get access to this resource during submission.
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*
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* The maximum amount of memory which could be mapped in this call depends
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* if overcommit is disabled or not. If overcommit is disabled than the max.
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* amount of memory to be pinned will be limited by left "free" size in total
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* amount of memory which could be locked simultaneously ("GART" size).
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*
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* Supported (theoretical) max. size of mapping is restricted only by
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* "GART" size.
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*
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* It is responsibility of caller to correctly specify access rights
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* on VA assignment.
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*/
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int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
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void *cpu, uint64_t size,
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struct amdgpu_bo_alloc_result *info);
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/**
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* Free previosuly allocated memory
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*
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@ -701,7 +727,6 @@ int amdgpu_bo_cpu_map(amdgpu_bo_handle buf_handle, void **cpu);
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*/
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int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle);
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/**
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* Wait until a buffer is not used by the device.
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*
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@ -713,7 +738,8 @@ int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle);
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* 1 GPU access is in fly or scheduled
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*
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* \return 0 - on success
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* <0 - AMD specific error code
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* >0 - AMD specific error code
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* <0 - Negative POSIX Error code
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*/
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int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle,
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uint64_t timeout_ns,
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@ -773,28 +799,6 @@ int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
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amdgpu_bo_handle *resources,
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uint8_t *resource_prios);
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/*
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* Special GPU Resources
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*
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*/
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/**
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* Query information about GDS
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*
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* \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
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* \param gds_info - \c [out] Pointer to structure to get GDS information
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*
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* \return 0 on success\n
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* >0 - AMD specific error code\n
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* <0 - Negative POSIX Error code
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*
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*/
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int amdgpu_query_gds_info(amdgpu_device_handle dev,
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struct amdgpu_gds_resource_info *gds_info);
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/*
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* GPU Execution context
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*
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@ -855,7 +859,6 @@ int amdgpu_cs_ctx_free(amdgpu_context_handle context);
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int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
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uint32_t *state, uint32_t *hangs);
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/*
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* Command Buffers Management
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*
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@ -929,13 +932,11 @@ int amdgpu_cs_submit(amdgpu_context_handle context,
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int amdgpu_cs_query_fence_status(struct amdgpu_cs_query_fence *fence,
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uint32_t *expired);
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/*
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* Query / Info API
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*
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*/
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/**
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* Query allocation size alignments
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*
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@ -956,8 +957,6 @@ int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
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struct amdgpu_buffer_size_alignments
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*info);
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/**
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* Query firmware versions
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*
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@ -977,8 +976,6 @@ int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
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unsigned ip_instance, unsigned index,
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uint32_t *version, uint32_t *feature);
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/**
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* Query the number of HW IP instances of a certain type.
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*
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@ -993,8 +990,6 @@ int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
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int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type,
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uint32_t *count);
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/**
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* Query engine information
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*
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@ -1014,9 +1009,6 @@ int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
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unsigned ip_instance,
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struct drm_amdgpu_info_hw_ip *info);
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/**
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* Query heap information
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*
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@ -1032,12 +1024,8 @@ int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
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* <0 - Negative POSIX Error code
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*
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*/
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int amdgpu_query_heap_info(amdgpu_device_handle dev,
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uint32_t heap,
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uint32_t flags,
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struct amdgpu_heap_info *info);
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int amdgpu_query_heap_info(amdgpu_device_handle dev, uint32_t heap,
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uint32_t flags, struct amdgpu_heap_info *info);
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/**
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* Get the CRTC ID from the mode object ID
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@ -1054,8 +1042,6 @@ int amdgpu_query_heap_info(amdgpu_device_handle dev,
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int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id,
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int32_t *result);
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/**
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* Query GPU H/w Info
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*
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@ -1073,8 +1059,6 @@ int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id,
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int amdgpu_query_gpu_info(amdgpu_device_handle dev,
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struct amdgpu_gpu_info *info);
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/**
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* Query hardware or driver information.
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*
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@ -1094,7 +1078,19 @@ int amdgpu_query_gpu_info(amdgpu_device_handle dev,
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int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
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unsigned size, void *value);
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/**
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* Query information about GDS
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*
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* \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
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* \param gds_info - \c [out] Pointer to structure to get GDS information
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*
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* \return 0 on success\n
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* >0 - AMD specific error code\n
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* <0 - Negative POSIX Error code
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*
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*/
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int amdgpu_query_gds_info(amdgpu_device_handle dev,
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struct amdgpu_gds_resource_info *gds_info);
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/**
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* Read a set of consecutive memory-mapped registers.
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@ -1118,46 +1114,4 @@ int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset,
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unsigned count, uint32_t instance, uint32_t flags,
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uint32_t *values);
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/**
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* Request GPU access to user allocated memory e.g. via "malloc"
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*
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* \param dev - [in] Device handle. See #amdgpu_device_initialize()
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* \param cpu - [in] CPU address of user allocated memory which we
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* want to map to GPU address space (make GPU accessible)
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* (This address must be correctly aligned).
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* \param size - [in] Size of allocation (must be correctly aligned)
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* \param amdgpu_bo_alloc_result - [out] Handle of allocation to be passed as resource
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* on submission and be used in other operations.(e.g. for VA submission)
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* ( Temporally defined amdgpu_bo_alloc_result as parameter for return mc address. )
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*
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*
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* \return 0 on success
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* >0 - AMD specific error code
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* <0 - Negative POSIX Error code
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*
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*
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* \note
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* This call doesn't guarantee that such memory will be persistently
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* "locked" / make non-pageable. The purpose of this call is to provide
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* opportunity for GPU get access to this resource during submission.
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*
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* The maximum amount of memory which could be mapped in this call depends
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* if overcommit is disabled or not. If overcommit is disabled than the max.
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* amount of memory to be pinned will be limited by left "free" size in total
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* amount of memory which could be locked simultaneously ("GART" size).
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*
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* Supported (theoretical) max. size of mapping is restricted only by
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* "GART" size.
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*
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* It is responsibility of caller to correctly specify access rights
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* on VA assignment.
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*/
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int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
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void *cpu,
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uint64_t size,
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struct amdgpu_bo_alloc_result *info);
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#endif /* #ifdef _AMDGPU_H_ */
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