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radeon: pad CS to 8 DW 

Aligns the IB to 8 DWs.  The aligns the IB to the
CP fetch size.  r6xx also require at least 4 DW
alignment to avoid a hw bug.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
main
Alex Deucher 2013-09-06 15:58:56 -04:00
parent 8a2e0fa917
commit 58d0088831
1 changed files with 3 additions and 0 deletions
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3
radeon/radeon_cs_gem.c
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@ -425,6 +425,9 @@ static int cs_gem_emit(struct radeon_cs_int *cs)
unsigned i;
int r;
while (cs->cdw & 7)
radeon_cs_write_dword((struct radeon_cs *)cs, 0x80000000);
#if CS_BOF_DUMP
cs_gem_dump_bof(cs);
#endif