VIA DRM: Stability enhancements and cleanups in via_dma.c Added explicit
licence notice in via_dma.cmain
Thomas Hellstrom
parent
02c35ec0a2
commit
590b230119
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@ -1,6 +1,4 @@
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/* via_dma.c -- DMA support for the VIA Unichrome/Pro
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*/
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/**************************************************************************
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*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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@ -11,7 +9,27 @@
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* Copyright 2004 The Unichrome project.
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* All Rights Reserved.
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*
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**************************************************************************/
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Various
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*/
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#include "drmP.h"
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#include "drm.h"
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@ -19,6 +37,28 @@
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#include "via_drv.h"
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#include "via_3d_reg.h"
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#define PCI_BUF_SIZE 512000
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#define CMDBUF_ALIGNMENT_SIZE (0x100)
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#define CMDBUF_ALIGNMENT_MASK (0xff)
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/* defines for VIA 3D registers */
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#define VIA_REG_STATUS 0x400
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#define VIA_REG_TRANSET 0x43C
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#define VIA_REG_TRANSPACE 0x440
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/* VIA_REG_STATUS(0x400): Engine Status */
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#define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */
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#define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */
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#define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */
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#define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */
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#define SetReg2DAGP(nReg, nData) { \
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*((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \
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*((uint32_t *)(vb) + 1) = (nData); \
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vb = ((uint32_t *)vb) + 2; \
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dev_priv->dma_low +=8; \
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}
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#define via_flush_write_combine() DRM_MEMORYBARRIER()
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#define VIA_OUT_RING_QW(w1,w2) \
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@ -26,12 +66,10 @@
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*vb++ = (w2); \
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dev_priv->dma_low += 8;
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#define PCI_BUF_SIZE 512000
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static char pci_buf[PCI_BUF_SIZE];
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static unsigned long pci_bufsiz = PCI_BUF_SIZE;
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static void via_cmdbuf_start(drm_via_private_t * dev_priv);
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static void via_cmdbuf_pause(drm_via_private_t * dev_priv);
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static void via_cmdbuf_reset(drm_via_private_t * dev_priv);
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@ -106,7 +144,7 @@ via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
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static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,
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unsigned int size)
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{
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if ((dev_priv->dma_low + size + 0x400) > dev_priv->dma_high) {
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if ((dev_priv->dma_low + size + 4*CMDBUF_ALIGNMENT_SIZE) > dev_priv->dma_high) {
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via_cmdbuf_rewind(dev_priv);
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}
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if (via_cmdbuf_wait(dev_priv, size) != 0) {
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@ -378,28 +416,6 @@ int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
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return 0;
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}
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/************************************************************************/
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#define CMDBUF_ALIGNMENT_SIZE (0x100)
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#define CMDBUF_ALIGNMENT_MASK (0xff)
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/* defines for VIA 3D registers */
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#define VIA_REG_STATUS 0x400
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#define VIA_REG_TRANSET 0x43C
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#define VIA_REG_TRANSPACE 0x440
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/* VIA_REG_STATUS(0x400): Engine Status */
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#define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */
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#define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */
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#define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */
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#define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */
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#define SetReg2DAGP(nReg, nData) { \
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*((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \
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*((uint32_t *)(vb) + 1) = (nData); \
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vb = ((uint32_t *)vb) + 2; \
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dev_priv->dma_low +=8; \
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}
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static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,
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uint32_t * vb, int qw_count)
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@ -447,6 +463,7 @@ static int via_hook_segment(drm_via_private_t *dev_priv,
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dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;
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while(! *dev_priv->last_pause_ptr);
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paused = 0;
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count = 20;
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@ -455,7 +472,8 @@ static int via_hook_segment(drm_via_private_t *dev_priv,
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uint32_t rgtr, ptr;
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rgtr = *(dev_priv->hw_addr_ptr);
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ptr = ((char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) +
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dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4 - 0x100;
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dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4 -
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CMDBUF_ALIGNMENT_SIZE;
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if (rgtr <= ptr) {
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DRM_ERROR("Command regulator\npaused at count %d, address %x, "
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"while current pause address is %x.\n"
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@ -467,16 +485,23 @@ static int via_hook_segment(drm_via_private_t *dev_priv,
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if (paused && !no_pci_fire) {
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uint32_t rgtr,ptr;
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uint32_t ptr_low;
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count = 1000000;
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while ((VIA_READ(VIA_REG_STATUS) & VIA_CMD_RGTR_BUSY) && count--);
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rgtr = *(dev_priv->hw_addr_ptr);
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ptr = ((char *)paused_at - dev_priv->dma_ptr) +
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dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
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if (rgtr <= ptr && rgtr >= ptr - 0x100) {
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ptr_low = (ptr > 3*CMDBUF_ALIGNMENT_SIZE) ?
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ptr - 3*CMDBUF_ALIGNMENT_SIZE : 0;
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if (rgtr <= ptr && rgtr >= ptr_low) {
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VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
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VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
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VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
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}
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}
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}
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return paused;
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}
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@ -659,7 +684,7 @@ static void via_cmdbuf_reset(drm_via_private_t * dev_priv)
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}
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/*
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* User interface to the space and lag function.
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* User interface to the space and lag functions.
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*/
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int
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@ -1,6 +1,4 @@
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/* via_dma.c -- DMA support for the VIA Unichrome/Pro
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*/
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/**************************************************************************
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*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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@ -11,7 +9,27 @@
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* Copyright 2004 The Unichrome project.
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* All Rights Reserved.
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*
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**************************************************************************/
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Various
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*/
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#include "via.h"
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#include "drmP.h"
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@ -20,6 +38,28 @@
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#include "via_drv.h"
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#include "via_3d_reg.h"
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#define PCI_BUF_SIZE 512000
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#define CMDBUF_ALIGNMENT_SIZE (0x100)
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#define CMDBUF_ALIGNMENT_MASK (0xff)
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/* defines for VIA 3D registers */
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#define VIA_REG_STATUS 0x400
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#define VIA_REG_TRANSET 0x43C
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#define VIA_REG_TRANSPACE 0x440
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/* VIA_REG_STATUS(0x400): Engine Status */
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#define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */
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#define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */
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#define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */
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#define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */
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#define SetReg2DAGP(nReg, nData) { \
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*((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \
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*((uint32_t *)(vb) + 1) = (nData); \
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vb = ((uint32_t *)vb) + 2; \
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dev_priv->dma_low +=8; \
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}
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#define via_flush_write_combine() DRM_MEMORYBARRIER()
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#define VIA_OUT_RING_QW(w1,w2) \
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@ -27,12 +67,10 @@
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*vb++ = (w2); \
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dev_priv->dma_low += 8;
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#define PCI_BUF_SIZE 512000
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static char pci_buf[PCI_BUF_SIZE];
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static unsigned long pci_bufsiz = PCI_BUF_SIZE;
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static void via_cmdbuf_start(drm_via_private_t * dev_priv);
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static void via_cmdbuf_pause(drm_via_private_t * dev_priv);
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static void via_cmdbuf_reset(drm_via_private_t * dev_priv);
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@ -107,7 +145,7 @@ via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
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static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,
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unsigned int size)
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{
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if ((dev_priv->dma_low + size + 0x400) > dev_priv->dma_high) {
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if ((dev_priv->dma_low + size + 4*CMDBUF_ALIGNMENT_SIZE) > dev_priv->dma_high) {
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via_cmdbuf_rewind(dev_priv);
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}
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if (via_cmdbuf_wait(dev_priv, size) != 0) {
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@ -379,28 +417,6 @@ int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
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return 0;
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}
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/************************************************************************/
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#define CMDBUF_ALIGNMENT_SIZE (0x100)
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#define CMDBUF_ALIGNMENT_MASK (0xff)
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/* defines for VIA 3D registers */
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#define VIA_REG_STATUS 0x400
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#define VIA_REG_TRANSET 0x43C
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#define VIA_REG_TRANSPACE 0x440
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/* VIA_REG_STATUS(0x400): Engine Status */
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#define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */
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#define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */
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#define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */
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#define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */
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#define SetReg2DAGP(nReg, nData) { \
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*((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \
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*((uint32_t *)(vb) + 1) = (nData); \
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vb = ((uint32_t *)vb) + 2; \
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dev_priv->dma_low +=8; \
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}
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static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,
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uint32_t * vb, int qw_count)
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@ -448,6 +464,7 @@ static int via_hook_segment(drm_via_private_t *dev_priv,
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dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;
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while(! *dev_priv->last_pause_ptr);
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paused = 0;
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count = 20;
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@ -456,7 +473,8 @@ static int via_hook_segment(drm_via_private_t *dev_priv,
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uint32_t rgtr, ptr;
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rgtr = *(dev_priv->hw_addr_ptr);
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ptr = ((char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) +
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dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4 - 0x100;
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dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4 -
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CMDBUF_ALIGNMENT_SIZE;
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if (rgtr <= ptr) {
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DRM_ERROR("Command regulator\npaused at count %d, address %x, "
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"while current pause address is %x.\n"
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@ -468,16 +486,23 @@ static int via_hook_segment(drm_via_private_t *dev_priv,
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if (paused && !no_pci_fire) {
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uint32_t rgtr,ptr;
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uint32_t ptr_low;
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count = 1000000;
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while ((VIA_READ(VIA_REG_STATUS) & VIA_CMD_RGTR_BUSY) && count--);
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rgtr = *(dev_priv->hw_addr_ptr);
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ptr = ((char *)paused_at - dev_priv->dma_ptr) +
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dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
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if (rgtr <= ptr && rgtr >= ptr - 0x100) {
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ptr_low = (ptr > 3*CMDBUF_ALIGNMENT_SIZE) ?
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ptr - 3*CMDBUF_ALIGNMENT_SIZE : 0;
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if (rgtr <= ptr && rgtr >= ptr_low) {
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VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
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VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
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VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
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}
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}
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}
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return paused;
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}
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@ -660,7 +685,7 @@ static void via_cmdbuf_reset(drm_via_private_t * dev_priv)
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}
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/*
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* User interface to the space and lag function.
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* User interface to the space and lag functions.
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*/
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int
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