remove files missed by merge
Alan Hourihane
parent
74ef13fd00
commit
59c07e447b
325
bsd/mga_drm.h
325
bsd/mga_drm.h
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@ -1,325 +0,0 @@
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/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
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* Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
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*
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* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
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* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Jeff Hartmann <jhartmann@valinux.com>
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* Keith Whitwell <keithw@valinux.com>
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*
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* Rewritten by:
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* Gareth Hughes <gareth@valinux.com>
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*/
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#ifndef __MGA_DRM_H__
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#define __MGA_DRM_H__
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/* WARNING: If you change any of these defines, make sure to change the
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* defines in the Xserver file (mga_sarea.h)
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*/
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#ifndef __MGA_SAREA_DEFINES__
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#define __MGA_SAREA_DEFINES__
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/* WARP pipe flags
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*/
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#define MGA_F 0x1 /* fog */
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#define MGA_A 0x2 /* alpha */
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#define MGA_S 0x4 /* specular */
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#define MGA_T2 0x8 /* multitexture */
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#define MGA_WARP_TGZ 0
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#define MGA_WARP_TGZF (MGA_F)
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#define MGA_WARP_TGZA (MGA_A)
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#define MGA_WARP_TGZAF (MGA_F|MGA_A)
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#define MGA_WARP_TGZS (MGA_S)
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#define MGA_WARP_TGZSF (MGA_S|MGA_F)
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#define MGA_WARP_TGZSA (MGA_S|MGA_A)
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#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A)
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#define MGA_WARP_T2GZ (MGA_T2)
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#define MGA_WARP_T2GZF (MGA_T2|MGA_F)
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#define MGA_WARP_T2GZA (MGA_T2|MGA_A)
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#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F)
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#define MGA_WARP_T2GZS (MGA_T2|MGA_S)
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#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F)
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#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A)
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#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A)
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#define MGA_MAX_G200_PIPES 8 /* no multitex */
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#define MGA_MAX_G400_PIPES 16
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#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
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#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */
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#define MGA_CARD_TYPE_G200 1
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#define MGA_CARD_TYPE_G400 2
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#define MGA_FRONT 0x1
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#define MGA_BACK 0x2
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#define MGA_DEPTH 0x4
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/* What needs to be changed for the current vertex dma buffer?
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*/
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#define MGA_UPLOAD_CONTEXT 0x1
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#define MGA_UPLOAD_TEX0 0x2
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#define MGA_UPLOAD_TEX1 0x4
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#define MGA_UPLOAD_PIPE 0x8
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#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */
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#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */
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#define MGA_UPLOAD_2D 0x40
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#define MGA_WAIT_AGE 0x80 /* handled client-side */
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#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */
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#if 0
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#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock
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quiescent */
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#endif
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/* 32 buffers of 64k each, total 2 meg.
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*/
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#define MGA_BUFFER_SIZE (1 << 16)
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#define MGA_NUM_BUFFERS 128
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/* Keep these small for testing.
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*/
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#define MGA_NR_SAREA_CLIPRECTS 8
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/* 2 heaps (1 for card, 1 for agp), each divided into upto 128
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* regions, subject to a minimum region size of (1<<16) == 64k.
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*
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* Clients may subdivide regions internally, but when sharing between
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* clients, the region size is the minimum granularity.
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*/
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#define MGA_CARD_HEAP 0
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#define MGA_AGP_HEAP 1
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#define MGA_NR_TEX_HEAPS 2
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#define MGA_NR_TEX_REGIONS 16
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#define MGA_LOG_MIN_TEX_REGION_SIZE 16
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#endif /* __MGA_SAREA_DEFINES__ */
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/* Setup registers for 3D context
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*/
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typedef struct {
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unsigned int dstorg;
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unsigned int maccess;
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unsigned int plnwt;
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unsigned int dwgctl;
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unsigned int alphactrl;
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unsigned int fogcolor;
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unsigned int wflag;
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unsigned int tdualstage0;
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unsigned int tdualstage1;
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unsigned int fcol;
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unsigned int stencil;
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unsigned int stencilctl;
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} drm_mga_context_regs_t;
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/* Setup registers for 2D, X server
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*/
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typedef struct {
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unsigned int pitch;
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} drm_mga_server_regs_t;
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/* Setup registers for each texture unit
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*/
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typedef struct {
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unsigned int texctl;
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unsigned int texctl2;
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unsigned int texfilter;
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unsigned int texbordercol;
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unsigned int texorg;
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unsigned int texwidth;
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unsigned int texheight;
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unsigned int texorg1;
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unsigned int texorg2;
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unsigned int texorg3;
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unsigned int texorg4;
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} drm_mga_texture_regs_t;
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/* General aging mechanism
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*/
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typedef struct {
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unsigned int head; /* Position of head pointer */
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unsigned int wrap; /* Primary DMA wrap count */
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} drm_mga_age_t;
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typedef struct _drm_mga_sarea {
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/* The channel for communication of state information to the kernel
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* on firing a vertex dma buffer.
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*/
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drm_mga_context_regs_t context_state;
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drm_mga_server_regs_t server_state;
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drm_mga_texture_regs_t tex_state[2];
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unsigned int warp_pipe;
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unsigned int dirty;
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unsigned int vertsize;
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/* The current cliprects, or a subset thereof.
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*/
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drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS];
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unsigned int nbox;
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/* Information about the most recently used 3d drawable. The
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* client fills in the req_* fields, the server fills in the
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* exported_ fields and puts the cliprects into boxes, above.
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*
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* The client clears the exported_drawable field before
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* clobbering the boxes data.
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*/
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unsigned int req_drawable; /* the X drawable id */
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unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */
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unsigned int exported_drawable;
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unsigned int exported_index;
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unsigned int exported_stamp;
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unsigned int exported_buffers;
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unsigned int exported_nfront;
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unsigned int exported_nback;
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int exported_back_x, exported_front_x, exported_w;
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int exported_back_y, exported_front_y, exported_h;
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drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS];
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/* Counters for aging textures and for client-side throttling.
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*/
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unsigned int status[4];
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unsigned int last_wrap;
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drm_mga_age_t last_frame;
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unsigned int last_enqueue; /* last time a buffer was enqueued */
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unsigned int last_dispatch; /* age of the most recently dispatched buffer */
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unsigned int last_quiescent; /* */
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/* LRU lists for texture memory in agp space and on the card.
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*/
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drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS+1];
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unsigned int texAge[MGA_NR_TEX_HEAPS];
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/* Mechanism to validate card state.
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*/
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int ctxOwner;
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} drm_mga_sarea_t;
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/* WARNING: If you change any of these defines, make sure to change the
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* defines in the Xserver file (xf86drmMga.h)
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*/
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/* MGA specific ioctls
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* The device specific ioctl range is 0x40 to 0x79.
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*/
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#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t)
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#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x41, drm_lock_t)
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#define DRM_IOCTL_MGA_RESET DRM_IO( 0x42)
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#define DRM_IOCTL_MGA_SWAP DRM_IO( 0x43)
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#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x44, drm_mga_clear_t)
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#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x45, drm_mga_vertex_t)
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#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t)
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#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x47, drm_mga_iload_t)
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#define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x48, drm_mga_blit_t)
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typedef struct _drm_mga_warp_index {
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int installed;
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unsigned long phys_addr;
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int size;
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} drm_mga_warp_index_t;
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typedef struct drm_mga_init {
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enum {
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MGA_INIT_DMA = 0x01,
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MGA_CLEANUP_DMA = 0x02
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} func;
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unsigned long sarea_priv_offset;
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int chipset;
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int sgram;
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unsigned int maccess;
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unsigned int fb_cpp;
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unsigned int front_offset, front_pitch;
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unsigned int back_offset, back_pitch;
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unsigned int depth_cpp;
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unsigned int depth_offset, depth_pitch;
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unsigned int texture_offset[MGA_NR_TEX_HEAPS];
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unsigned int texture_size[MGA_NR_TEX_HEAPS];
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unsigned long fb_offset;
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unsigned long mmio_offset;
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unsigned long status_offset;
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unsigned long warp_offset;
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unsigned long primary_offset;
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unsigned long buffers_offset;
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} drm_mga_init_t;
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typedef struct drm_mga_fullscreen {
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enum {
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MGA_INIT_FULLSCREEN = 0x01,
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MGA_CLEANUP_FULLSCREEN = 0x02
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} func;
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} drm_mga_fullscreen_t;
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typedef struct drm_mga_clear {
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unsigned int flags;
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unsigned int clear_color;
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unsigned int clear_depth;
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unsigned int color_mask;
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unsigned int depth_mask;
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} drm_mga_clear_t;
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typedef struct drm_mga_vertex {
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int idx; /* buffer to queue */
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int used; /* bytes in use */
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int discard; /* client finished with buffer? */
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} drm_mga_vertex_t;
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typedef struct drm_mga_indices {
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int idx; /* buffer to queue */
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unsigned int start;
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unsigned int end;
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int discard; /* client finished with buffer? */
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} drm_mga_indices_t;
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typedef struct drm_mga_iload {
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int idx;
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unsigned int dstorg;
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unsigned int length;
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} drm_mga_iload_t;
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typedef struct _drm_mga_blit {
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unsigned int planemask;
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unsigned int srcorg;
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unsigned int dstorg;
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int src_pitch, dst_pitch;
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int delta_sx, delta_sy;
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int delta_dx, delta_dy;
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int height, ydir; /* flip image vertically */
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int source_pitch, dest_pitch;
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} drm_mga_blit_t;
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#endif
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308
bsd/r128_drm.h
308
bsd/r128_drm.h
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@ -1,308 +0,0 @@
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/* r128_drm.h -- Public header for the r128 driver -*- linux-c -*-
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* Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com
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*
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* Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
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* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
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* to deal in the Software without restriction, including without limitation
|
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
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* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
|
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* Software.
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*
|
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Gareth Hughes <gareth@valinux.com>
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* Kevin E. Martin <martin@valinux.com>
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*/
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#ifndef __R128_DRM_H__
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#define __R128_DRM_H__
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/* WARNING: If you change any of these defines, make sure to change the
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* defines in the X server file (r128_sarea.h)
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*/
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#ifndef __R128_SAREA_DEFINES__
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#define __R128_SAREA_DEFINES__
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/* What needs to be changed for the current vertex buffer?
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*/
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#define R128_UPLOAD_CONTEXT 0x001
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#define R128_UPLOAD_SETUP 0x002
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#define R128_UPLOAD_TEX0 0x004
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#define R128_UPLOAD_TEX1 0x008
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#define R128_UPLOAD_TEX0IMAGES 0x010
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#define R128_UPLOAD_TEX1IMAGES 0x020
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#define R128_UPLOAD_CORE 0x040
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#define R128_UPLOAD_MASKS 0x080
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#define R128_UPLOAD_WINDOW 0x100
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#define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */
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#define R128_REQUIRE_QUIESCENCE 0x400
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#define R128_UPLOAD_ALL 0x7ff
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#define R128_FRONT 0x1
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#define R128_BACK 0x2
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#define R128_DEPTH 0x4
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/* Primitive types
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*/
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#define R128_POINTS 0x1
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#define R128_LINES 0x2
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#define R128_LINE_STRIP 0x3
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#define R128_TRIANGLES 0x4
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#define R128_TRIANGLE_FAN 0x5
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#define R128_TRIANGLE_STRIP 0x6
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/* Vertex/indirect buffer size
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*/
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#define R128_BUFFER_SIZE 16384
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/* Byte offsets for indirect buffer data
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*/
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#define R128_INDEX_PRIM_OFFSET 20
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#define R128_HOSTDATA_BLIT_OFFSET 32
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/* Keep these small for testing.
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*/
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#define R128_NR_SAREA_CLIPRECTS 12
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/* There are 2 heaps (local/AGP). Each region within a heap is a
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* minimum of 64k, and there are at most 64 of them per heap.
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*/
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#define R128_LOCAL_TEX_HEAP 0
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#define R128_AGP_TEX_HEAP 1
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#define R128_NR_TEX_HEAPS 2
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#define R128_NR_TEX_REGIONS 64
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#define R128_LOG_TEX_GRANULARITY 16
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#define R128_NR_CONTEXT_REGS 12
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#define R128_MAX_TEXTURE_LEVELS 11
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#define R128_MAX_TEXTURE_UNITS 2
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#endif /* __R128_SAREA_DEFINES__ */
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typedef struct {
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/* Context state - can be written in one large chunk */
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unsigned int dst_pitch_offset_c;
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unsigned int dp_gui_master_cntl_c;
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unsigned int sc_top_left_c;
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unsigned int sc_bottom_right_c;
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unsigned int z_offset_c;
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unsigned int z_pitch_c;
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unsigned int z_sten_cntl_c;
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unsigned int tex_cntl_c;
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unsigned int misc_3d_state_cntl_reg;
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unsigned int texture_clr_cmp_clr_c;
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unsigned int texture_clr_cmp_msk_c;
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unsigned int fog_color_c;
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/* Texture state */
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unsigned int tex_size_pitch_c;
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unsigned int constant_color_c;
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/* Setup state */
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unsigned int pm4_vc_fpu_setup;
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unsigned int setup_cntl;
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||||
|
||||
/* Mask state */
|
||||
unsigned int dp_write_mask;
|
||||
unsigned int sten_ref_mask_c;
|
||||
unsigned int plane_3d_mask_c;
|
||||
|
||||
/* Window state */
|
||||
unsigned int window_xy_offset;
|
||||
|
||||
/* Core state */
|
||||
unsigned int scale_3d_cntl;
|
||||
} drm_r128_context_regs_t;
|
||||
|
||||
/* Setup registers for each texture unit
|
||||
*/
|
||||
typedef struct {
|
||||
unsigned int tex_cntl;
|
||||
unsigned int tex_combine_cntl;
|
||||
unsigned int tex_size_pitch;
|
||||
unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
|
||||
unsigned int tex_border_color;
|
||||
} drm_r128_texture_regs_t;
|
||||
|
||||
|
||||
typedef struct drm_r128_sarea {
|
||||
/* The channel for communication of state information to the kernel
|
||||
* on firing a vertex buffer.
|
||||
*/
|
||||
drm_r128_context_regs_t context_state;
|
||||
drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS];
|
||||
unsigned int dirty;
|
||||
unsigned int vertsize;
|
||||
unsigned int vc_format;
|
||||
|
||||
/* The current cliprects, or a subset thereof.
|
||||
*/
|
||||
drm_clip_rect_t boxes[R128_NR_SAREA_CLIPRECTS];
|
||||
unsigned int nbox;
|
||||
|
||||
/* Counters for client-side throttling of rendering clients.
|
||||
*/
|
||||
unsigned int last_frame;
|
||||
unsigned int last_dispatch;
|
||||
|
||||
drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS+1];
|
||||
int tex_age[R128_NR_TEX_HEAPS];
|
||||
int ctx_owner;
|
||||
} drm_r128_sarea_t;
|
||||
|
||||
|
||||
/* WARNING: If you change any of these defines, make sure to change the
|
||||
* defines in the Xserver file (xf86drmR128.h)
|
||||
*/
|
||||
|
||||
/* Rage 128 specific ioctls
|
||||
* The device specific ioctl range is 0x40 to 0x79.
|
||||
*/
|
||||
#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
|
||||
#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41)
|
||||
#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t)
|
||||
#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
|
||||
#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
|
||||
#define DRM_IOCTL_R128_RESET DRM_IO( 0x46)
|
||||
#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47)
|
||||
#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t)
|
||||
#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t)
|
||||
#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t)
|
||||
#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t)
|
||||
#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t)
|
||||
#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t)
|
||||
#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(0x4f, drm_r128_indirect_t)
|
||||
#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x50, drm_r128_fullscreen_t)
|
||||
#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( 0x51, drm_r128_clear2_t)
|
||||
|
||||
typedef struct drm_r128_init {
|
||||
enum {
|
||||
R128_INIT_CCE = 0x01,
|
||||
R128_CLEANUP_CCE = 0x02
|
||||
} func;
|
||||
#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
|
||||
int sarea_priv_offset;
|
||||
#else
|
||||
unsigned long sarea_priv_offset;
|
||||
#endif
|
||||
int is_pci;
|
||||
int cce_mode;
|
||||
int cce_secure;
|
||||
int ring_size;
|
||||
int usec_timeout;
|
||||
|
||||
unsigned int fb_bpp;
|
||||
unsigned int front_offset, front_pitch;
|
||||
unsigned int back_offset, back_pitch;
|
||||
unsigned int depth_bpp;
|
||||
unsigned int depth_offset, depth_pitch;
|
||||
unsigned int span_offset;
|
||||
|
||||
#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
|
||||
unsigned int fb_offset;
|
||||
unsigned int mmio_offset;
|
||||
unsigned int ring_offset;
|
||||
unsigned int ring_rptr_offset;
|
||||
unsigned int buffers_offset;
|
||||
unsigned int agp_textures_offset;
|
||||
#else
|
||||
unsigned long fb_offset;
|
||||
unsigned long mmio_offset;
|
||||
unsigned long ring_offset;
|
||||
unsigned long ring_rptr_offset;
|
||||
unsigned long buffers_offset;
|
||||
unsigned long agp_textures_offset;
|
||||
#endif
|
||||
} drm_r128_init_t;
|
||||
|
||||
typedef struct drm_r128_cce_stop {
|
||||
int flush;
|
||||
int idle;
|
||||
} drm_r128_cce_stop_t;
|
||||
|
||||
typedef struct drm_r128_clear {
|
||||
unsigned int flags;
|
||||
#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
|
||||
int x, y, w, h;
|
||||
#endif
|
||||
unsigned int clear_color;
|
||||
unsigned int clear_depth;
|
||||
#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
|
||||
unsigned int color_mask;
|
||||
unsigned int depth_mask;
|
||||
#endif
|
||||
} drm_r128_clear_t;
|
||||
|
||||
typedef struct drm_r128_vertex {
|
||||
int prim;
|
||||
int idx; /* Index of vertex buffer */
|
||||
int count; /* Number of vertices in buffer */
|
||||
int discard; /* Client finished with buffer? */
|
||||
} drm_r128_vertex_t;
|
||||
|
||||
typedef struct drm_r128_indices {
|
||||
int prim;
|
||||
int idx;
|
||||
int start;
|
||||
int end;
|
||||
int discard; /* Client finished with buffer? */
|
||||
} drm_r128_indices_t;
|
||||
|
||||
typedef struct drm_r128_blit {
|
||||
int idx;
|
||||
int pitch;
|
||||
int offset;
|
||||
int format;
|
||||
unsigned short x, y;
|
||||
unsigned short width, height;
|
||||
} drm_r128_blit_t;
|
||||
|
||||
typedef struct drm_r128_depth {
|
||||
enum {
|
||||
R128_WRITE_SPAN = 0x01,
|
||||
R128_WRITE_PIXELS = 0x02,
|
||||
R128_READ_SPAN = 0x03,
|
||||
R128_READ_PIXELS = 0x04
|
||||
} func;
|
||||
int n;
|
||||
int *x;
|
||||
int *y;
|
||||
unsigned int *buffer;
|
||||
unsigned char *mask;
|
||||
} drm_r128_depth_t;
|
||||
|
||||
typedef struct drm_r128_stipple {
|
||||
unsigned int *mask;
|
||||
} drm_r128_stipple_t;
|
||||
|
||||
typedef struct drm_r128_indirect {
|
||||
int idx;
|
||||
int start;
|
||||
int end;
|
||||
int discard;
|
||||
} drm_r128_indirect_t;
|
||||
|
||||
typedef struct drm_r128_fullscreen {
|
||||
enum {
|
||||
R128_INIT_FULLSCREEN = 0x01,
|
||||
R128_CLEANUP_FULLSCREEN = 0x02
|
||||
} func;
|
||||
} drm_r128_fullscreen_t;
|
||||
|
||||
#endif
|
||||
370
bsd/radeon_drm.h
370
bsd/radeon_drm.h
|
|
@ -1,370 +0,0 @@
|
|||
/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
|
||||
*
|
||||
* Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
|
||||
* Copyright 2000 VA Linux Systems, Inc., Fremont, California.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Kevin E. Martin <martin@valinux.com>
|
||||
* Gareth Hughes <gareth@valinux.com>
|
||||
* Keith Whitwell <keith_whitwell@yahoo.com>
|
||||
*/
|
||||
|
||||
#ifndef __RADEON_DRM_H__
|
||||
#define __RADEON_DRM_H__
|
||||
|
||||
/* WARNING: If you change any of these defines, make sure to change the
|
||||
* defines in the X server file (radeon_sarea.h)
|
||||
*/
|
||||
#ifndef __RADEON_SAREA_DEFINES__
|
||||
#define __RADEON_SAREA_DEFINES__
|
||||
|
||||
/* What needs to be changed for the current vertex buffer?
|
||||
*/
|
||||
#define RADEON_UPLOAD_CONTEXT 0x00000001
|
||||
#define RADEON_UPLOAD_VERTFMT 0x00000002
|
||||
#define RADEON_UPLOAD_LINE 0x00000004
|
||||
#define RADEON_UPLOAD_BUMPMAP 0x00000008
|
||||
#define RADEON_UPLOAD_MASKS 0x00000010
|
||||
#define RADEON_UPLOAD_VIEWPORT 0x00000020
|
||||
#define RADEON_UPLOAD_SETUP 0x00000040
|
||||
#define RADEON_UPLOAD_TCL 0x00000080
|
||||
#define RADEON_UPLOAD_MISC 0x00000100
|
||||
#define RADEON_UPLOAD_TEX0 0x00000200
|
||||
#define RADEON_UPLOAD_TEX1 0x00000400
|
||||
#define RADEON_UPLOAD_TEX2 0x00000800
|
||||
#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
|
||||
#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
|
||||
#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
|
||||
#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
|
||||
#define RADEON_REQUIRE_QUIESCENCE 0x00010000
|
||||
#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
|
||||
#define RADEON_UPLOAD_ALL 0x0002ffff
|
||||
#define RADEON_UPLOAD_CONTEXT_ALL 0x000201ff
|
||||
|
||||
#define RADEON_FRONT 0x1
|
||||
#define RADEON_BACK 0x2
|
||||
#define RADEON_DEPTH 0x4
|
||||
#define RADEON_STENCIL 0x8
|
||||
|
||||
/* Primitive types
|
||||
*/
|
||||
#define RADEON_POINTS 0x1
|
||||
#define RADEON_LINES 0x2
|
||||
#define RADEON_LINE_STRIP 0x3
|
||||
#define RADEON_TRIANGLES 0x4
|
||||
#define RADEON_TRIANGLE_FAN 0x5
|
||||
#define RADEON_TRIANGLE_STRIP 0x6
|
||||
|
||||
/* Vertex/indirect buffer size
|
||||
*/
|
||||
#define RADEON_BUFFER_SIZE 65536
|
||||
|
||||
/* Byte offsets for indirect buffer data
|
||||
*/
|
||||
#define RADEON_INDEX_PRIM_OFFSET 20
|
||||
#define RADEON_HOSTDATA_BLIT_OFFSET 32
|
||||
|
||||
#define RADEON_SCRATCH_REG_OFFSET 32
|
||||
|
||||
#define RADEON_NR_SAREA_CLIPRECTS 12
|
||||
|
||||
/* There are 2 heaps (local/AGP). Each region within a heap is a
|
||||
* minimum of 64k, and there are at most 64 of them per heap.
|
||||
*/
|
||||
#define RADEON_LOCAL_TEX_HEAP 0
|
||||
#define RADEON_AGP_TEX_HEAP 1
|
||||
#define RADEON_NR_TEX_HEAPS 2
|
||||
#define RADEON_NR_TEX_REGIONS 64
|
||||
#define RADEON_LOG_TEX_GRANULARITY 16
|
||||
|
||||
#define RADEON_MAX_TEXTURE_LEVELS 12
|
||||
#define RADEON_MAX_TEXTURE_UNITS 3
|
||||
|
||||
#endif /* __RADEON_SAREA_DEFINES__ */
|
||||
|
||||
typedef struct {
|
||||
unsigned int red;
|
||||
unsigned int green;
|
||||
unsigned int blue;
|
||||
unsigned int alpha;
|
||||
} radeon_color_regs_t;
|
||||
|
||||
typedef struct {
|
||||
/* Context state */
|
||||
unsigned int pp_misc; /* 0x1c14 */
|
||||
unsigned int pp_fog_color;
|
||||
unsigned int re_solid_color;
|
||||
unsigned int rb3d_blendcntl;
|
||||
unsigned int rb3d_depthoffset;
|
||||
unsigned int rb3d_depthpitch;
|
||||
unsigned int rb3d_zstencilcntl;
|
||||
|
||||
unsigned int pp_cntl; /* 0x1c38 */
|
||||
unsigned int rb3d_cntl;
|
||||
unsigned int rb3d_coloroffset;
|
||||
unsigned int re_width_height;
|
||||
unsigned int rb3d_colorpitch;
|
||||
unsigned int se_cntl;
|
||||
|
||||
/* Vertex format state */
|
||||
unsigned int se_coord_fmt; /* 0x1c50 */
|
||||
|
||||
/* Line state */
|
||||
unsigned int re_line_pattern; /* 0x1cd0 */
|
||||
unsigned int re_line_state;
|
||||
|
||||
unsigned int se_line_width; /* 0x1db8 */
|
||||
|
||||
/* Bumpmap state */
|
||||
unsigned int pp_lum_matrix; /* 0x1d00 */
|
||||
|
||||
unsigned int pp_rot_matrix_0; /* 0x1d58 */
|
||||
unsigned int pp_rot_matrix_1;
|
||||
|
||||
/* Mask state */
|
||||
unsigned int rb3d_stencilrefmask; /* 0x1d7c */
|
||||
unsigned int rb3d_ropcntl;
|
||||
unsigned int rb3d_planemask;
|
||||
|
||||
/* Viewport state */
|
||||
unsigned int se_vport_xscale; /* 0x1d98 */
|
||||
unsigned int se_vport_xoffset;
|
||||
unsigned int se_vport_yscale;
|
||||
unsigned int se_vport_yoffset;
|
||||
unsigned int se_vport_zscale;
|
||||
unsigned int se_vport_zoffset;
|
||||
|
||||
/* Setup state */
|
||||
unsigned int se_cntl_status; /* 0x2140 */
|
||||
|
||||
/* Misc state */
|
||||
unsigned int re_top_left; /* 0x26c0 */
|
||||
unsigned int re_misc;
|
||||
} drm_radeon_context_regs_t;
|
||||
|
||||
typedef struct {
|
||||
/* Zbias state */
|
||||
unsigned int se_zbias_factor; /* 0x1dac */
|
||||
unsigned int se_zbias_constant;
|
||||
} drm_radeon_context2_regs_t;
|
||||
|
||||
|
||||
/* Setup registers for each texture unit
|
||||
*/
|
||||
typedef struct {
|
||||
unsigned int pp_txfilter;
|
||||
unsigned int pp_txformat;
|
||||
unsigned int pp_txoffset;
|
||||
unsigned int pp_txcblend;
|
||||
unsigned int pp_txablend;
|
||||
unsigned int pp_tfactor;
|
||||
unsigned int pp_border_color;
|
||||
} drm_radeon_texture_regs_t;
|
||||
|
||||
/* Space is crucial; there is some redunancy here:
|
||||
*/
|
||||
typedef struct {
|
||||
unsigned int start;
|
||||
unsigned int finish;
|
||||
unsigned int prim:8;
|
||||
unsigned int stateidx:8;
|
||||
unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
|
||||
unsigned int vc_format; /* vertex format */
|
||||
} drm_radeon_prim_t;
|
||||
|
||||
typedef struct {
|
||||
drm_radeon_context_regs_t context;
|
||||
drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
|
||||
drm_radeon_context2_regs_t context2;
|
||||
unsigned int dirty;
|
||||
} drm_radeon_state_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
unsigned char next, prev;
|
||||
unsigned char in_use;
|
||||
int age;
|
||||
} drm_radeon_tex_region_t;
|
||||
|
||||
typedef struct {
|
||||
/* The channel for communication of state information to the
|
||||
* kernel on firing a vertex buffer with either of the
|
||||
* obsoleted vertex/index ioctls.
|
||||
*/
|
||||
drm_radeon_context_regs_t context_state;
|
||||
drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
|
||||
unsigned int dirty;
|
||||
unsigned int vertsize;
|
||||
unsigned int vc_format;
|
||||
|
||||
/* The current cliprects, or a subset thereof.
|
||||
*/
|
||||
drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS];
|
||||
unsigned int nbox;
|
||||
|
||||
/* Counters for client-side throttling of rendering clients.
|
||||
*/
|
||||
unsigned int last_frame;
|
||||
unsigned int last_dispatch;
|
||||
unsigned int last_clear;
|
||||
|
||||
drm_radeon_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
|
||||
int tex_age[RADEON_NR_TEX_HEAPS];
|
||||
int ctx_owner;
|
||||
} drm_radeon_sarea_t;
|
||||
|
||||
|
||||
/* WARNING: If you change any of these defines, make sure to change the
|
||||
* defines in the Xserver file (xf86drmRadeon.h)
|
||||
*
|
||||
* KW: actually it's illegal to change any of this (backwards compatibility).
|
||||
*/
|
||||
|
||||
/* Radeon specific ioctls
|
||||
* The device specific ioctl range is 0x40 to 0x79.
|
||||
*/
|
||||
#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t)
|
||||
#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41)
|
||||
#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t)
|
||||
#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43)
|
||||
#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44)
|
||||
#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45)
|
||||
#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t)
|
||||
#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47)
|
||||
#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t)
|
||||
#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t)
|
||||
#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t)
|
||||
#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t)
|
||||
#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t)
|
||||
#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t)
|
||||
#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( 0x4f, drm_radeon_vertex_t)
|
||||
|
||||
typedef struct drm_radeon_init {
|
||||
enum {
|
||||
RADEON_INIT_CP = 0x01,
|
||||
RADEON_CLEANUP_CP = 0x02
|
||||
} func;
|
||||
unsigned long sarea_priv_offset;
|
||||
int is_pci;
|
||||
int cp_mode;
|
||||
int agp_size;
|
||||
int ring_size;
|
||||
int usec_timeout;
|
||||
|
||||
unsigned int fb_bpp;
|
||||
unsigned int front_offset, front_pitch;
|
||||
unsigned int back_offset, back_pitch;
|
||||
unsigned int depth_bpp;
|
||||
unsigned int depth_offset, depth_pitch;
|
||||
|
||||
unsigned long fb_offset;
|
||||
unsigned long mmio_offset;
|
||||
unsigned long ring_offset;
|
||||
unsigned long ring_rptr_offset;
|
||||
unsigned long buffers_offset;
|
||||
unsigned long agp_textures_offset;
|
||||
} drm_radeon_init_t;
|
||||
|
||||
typedef struct drm_radeon_cp_stop {
|
||||
int flush;
|
||||
int idle;
|
||||
} drm_radeon_cp_stop_t;
|
||||
|
||||
typedef struct drm_radeon_fullscreen {
|
||||
enum {
|
||||
RADEON_INIT_FULLSCREEN = 0x01,
|
||||
RADEON_CLEANUP_FULLSCREEN = 0x02
|
||||
} func;
|
||||
} drm_radeon_fullscreen_t;
|
||||
|
||||
#define CLEAR_X1 0
|
||||
#define CLEAR_Y1 1
|
||||
#define CLEAR_X2 2
|
||||
#define CLEAR_Y2 3
|
||||
#define CLEAR_DEPTH 4
|
||||
|
||||
typedef union drm_radeon_clear_rect {
|
||||
float f[5];
|
||||
unsigned int ui[5];
|
||||
} drm_radeon_clear_rect_t;
|
||||
|
||||
typedef struct drm_radeon_clear {
|
||||
unsigned int flags;
|
||||
unsigned int clear_color;
|
||||
unsigned int clear_depth;
|
||||
unsigned int color_mask;
|
||||
unsigned int depth_mask; /* misnamed field: should be stencil */
|
||||
drm_radeon_clear_rect_t *depth_boxes;
|
||||
} drm_radeon_clear_t;
|
||||
|
||||
typedef struct drm_radeon_vertex {
|
||||
int prim;
|
||||
int idx; /* Index of vertex buffer */
|
||||
int count; /* Number of vertices in buffer */
|
||||
int discard; /* Client finished with buffer? */
|
||||
} drm_radeon_vertex_t;
|
||||
|
||||
typedef struct drm_radeon_vertex2 {
|
||||
int idx; /* Index of vertex buffer */
|
||||
int discard; /* Client finished with buffer? */
|
||||
int nr_states;
|
||||
drm_radeon_state_t *state;
|
||||
int nr_prims;
|
||||
drm_radeon_prim_t *prim;
|
||||
} drm_radeon_vertex2_t;
|
||||
|
||||
typedef struct drm_radeon_indices {
|
||||
int prim;
|
||||
int idx;
|
||||
int start;
|
||||
int end;
|
||||
int discard; /* Client finished with buffer? */
|
||||
} drm_radeon_indices_t;
|
||||
|
||||
typedef struct drm_radeon_tex_image {
|
||||
unsigned int x, y; /* Blit coordinates */
|
||||
unsigned int width, height;
|
||||
const void *data;
|
||||
} drm_radeon_tex_image_t;
|
||||
|
||||
typedef struct drm_radeon_texture {
|
||||
int offset;
|
||||
int pitch;
|
||||
int format;
|
||||
int width; /* Texture image coordinates */
|
||||
int height;
|
||||
drm_radeon_tex_image_t *image;
|
||||
} drm_radeon_texture_t;
|
||||
|
||||
typedef struct drm_radeon_stipple {
|
||||
unsigned int *mask;
|
||||
} drm_radeon_stipple_t;
|
||||
|
||||
typedef struct drm_radeon_indirect {
|
||||
int idx;
|
||||
int start;
|
||||
int end;
|
||||
int discard;
|
||||
} drm_radeon_indirect_t;
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue