preserve CRTC{,2}_OFFSET_CNTL in 2D driver to avoid bad effects when
pageflipping after a mode switch
take current page into account in AdjustFrame(); writing the CRTC offset
via the CP was probably a bad idea as this can happen asynchronously,
reverted
take frame offset into account when flipping pages
handle CRTC2 as well for pageflipping (untested)
preserve GEN_INT_CNTL on mode switches to prevent interrupts from getting
disabled
main
Michel Daenzer
parent
10900dab7c
commit
5e1b8ed88a
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@ -19,6 +19,7 @@ all::
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clean::
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$(MAKE) -f Makefile.bsd clean
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LinkSourceFile(drm_sarea.h,$(XF86OSSRC)/shared/drm/kernel)
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LinkSourceFile(mga.h,$(XF86OSSRC)/shared/drm/kernel)
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LinkSourceFile(mga_dma.c,$(XF86OSSRC)/shared/drm/kernel)
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LinkSourceFile(mga_drm.h,$(XF86OSSRC)/shared/drm/kernel)
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@ -44,7 +44,7 @@ LIBS =
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DRMTEMPLATES = drm_auth.h drm_bufs.h drm_context.h drm_dma.h drm_drawable.h \
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drm_drv.h drm_fops.h drm_init.h drm_ioctl.h drm_lists.h \
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drm_lock.h drm_memory.h drm_proc.h drm_stub.h drm_vm.h
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DRMHEADERS = drm.h drmP.h
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DRMHEADERS = drm.h drmP.h drm_sarea.h
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GAMMAOBJS = gamma_drv.o gamma_dma.o
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GAMMAHEADERS = gamma_drv.h $(DRMHEADERS) $(DRMTEMPLATES)
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@ -0,0 +1,57 @@
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/* sarea.h -- SAREA definitions -*- linux-c -*-
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*
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* Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Michel Dänzer <michel@daenzer.net>
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*/
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#ifndef _DRM_SAREA_H_
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#define _DRM_SAREA_H_
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#define SAREA_MAX_DRAWABLES 256
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typedef struct _drm_sarea_drawable_t {
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unsigned int stamp;
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unsigned int flags;
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} drm_sarea_drawable_t;
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typedef struct _dri_sarea_frame_t {
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unsigned int x;
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unsigned int y;
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unsigned int width;
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unsigned int height;
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unsigned int fullscreen;
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} drm_sarea_frame_t;
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typedef struct _drm_sarea_t {
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/* first thing is always the drm locking structure */
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drm_hw_lock_t lock;
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/* NOT_DONE: Use readers/writer lock for drawable_lock */
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drm_hw_lock_t drawable_lock;
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drm_sarea_drawable_t drawableTable[SAREA_MAX_DRAWABLES];
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drm_sarea_frame_t frame;
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drm_context_t dummy_context;
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} drm_sarea_t;
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#endif /* _DRM_SAREA_H_ */
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@ -355,6 +355,7 @@ typedef struct {
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int ctx_owner;
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int pfState; /* number of 3d windows (0,1,2ormore) */
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int pfCurrentPage; /* which buffer is being displayed? */
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int crtc2_base; /* CRTC2 frame offset */
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} drm_radeon_sarea_t;
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@ -109,8 +109,6 @@ typedef struct drm_radeon_private {
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int do_boxes;
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int page_flipping;
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int current_page;
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u32 crtc_offset;
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u32 crtc_offset_cntl;
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u32 color_fmt;
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unsigned int front_offset;
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@ -230,6 +228,8 @@ extern int radeon_emit_irq(drm_device_t *dev);
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#define RADEON_CRTC_OFFSET_CNTL 0x0228
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# define RADEON_CRTC_TILE_EN (1 << 15)
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# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
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#define RADEON_CRTC2_OFFSET 0x0324
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#define RADEON_CRTC2_OFFSET_CNTL 0x0328
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#define RADEON_RB3D_COLORPITCH 0x1c48
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@ -30,6 +30,7 @@
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#include "radeon.h"
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#include "drmP.h"
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#include "drm.h"
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#include "drm_sarea.h"
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#include "radeon_drm.h"
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#include "radeon_drv.h"
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@ -803,6 +804,9 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev )
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static void radeon_cp_dispatch_flip( drm_device_t *dev )
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_sarea_t *sarea = (drm_sarea_t *)dev_priv->sarea->handle;
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int offset = (dev_priv->current_page == 1)
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? dev_priv->front_offset : dev_priv->back_offset;
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RING_LOCALS;
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DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n",
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__FUNCTION__,
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@ -816,18 +820,17 @@ static void radeon_cp_dispatch_flip( drm_device_t *dev )
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radeon_cp_performance_boxes( dev_priv );
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}
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BEGIN_RING( 4 );
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/* Update the frame offsets for both CRTCs
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*/
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BEGIN_RING( 6 );
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RADEON_WAIT_UNTIL_3D_IDLE();
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OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET, 0 ) );
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if ( dev_priv->current_page == 0 ) {
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OUT_RING( dev_priv->back_offset );
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dev_priv->current_page = 1;
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} else {
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OUT_RING( dev_priv->front_offset );
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dev_priv->current_page = 0;
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}
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OUT_RING_REG( RADEON_CRTC_OFFSET, ( ( sarea->frame.y * dev_priv->front_pitch
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+ sarea->frame.x
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* ( dev_priv->color_fmt - 2 ) ) & ~7 )
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+ offset );
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OUT_RING_REG( RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base
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+ offset );
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ADVANCE_RING();
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@ -836,7 +839,8 @@ static void radeon_cp_dispatch_flip( drm_device_t *dev )
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* performing the swapbuffer ioctl.
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*/
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dev_priv->sarea_priv->last_frame++;
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dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
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dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
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1 - dev_priv->current_page;
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BEGIN_RING( 2 );
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@ -1304,12 +1308,12 @@ static int radeon_do_init_pageflip( drm_device_t *dev )
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DRM_DEBUG( "\n" );
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dev_priv->crtc_offset_cntl = RADEON_READ( RADEON_CRTC_OFFSET_CNTL );
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BEGIN_RING( 4 );
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BEGIN_RING( 6 );
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RADEON_WAIT_UNTIL_3D_IDLE();
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OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET_CNTL, 0 ) );
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OUT_RING( dev_priv->crtc_offset_cntl | RADEON_CRTC_OFFSET_FLIP_CNTL );
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OUT_RING( RADEON_READ( RADEON_CRTC_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL );
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OUT_RING( CP_PACKET0( RADEON_CRTC2_OFFSET_CNTL, 0 ) );
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OUT_RING( RADEON_READ( RADEON_CRTC2_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL );
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ADVANCE_RING();
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dev_priv->page_flipping = 1;
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@ -1330,10 +1334,6 @@ int radeon_do_cleanup_pageflip( drm_device_t *dev )
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if (dev_priv->current_page != 0)
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radeon_cp_dispatch_flip( dev );
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/* FIXME: If the X server changes screen resolution, it
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* clobbers the value of RADEON_CRTC_OFFSET_CNTL, above,
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* leading to a flashing efect.
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*/
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dev_priv->page_flipping = 0;
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return 0;
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}
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@ -0,0 +1,57 @@
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/* sarea.h -- SAREA definitions -*- linux-c -*-
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*
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* Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
|
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
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* and/or sell copies of the Software, and to permit persons to whom the
|
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Michel Dänzer <michel@daenzer.net>
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*/
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#ifndef _DRM_SAREA_H_
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#define _DRM_SAREA_H_
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#define SAREA_MAX_DRAWABLES 256
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typedef struct _drm_sarea_drawable_t {
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unsigned int stamp;
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unsigned int flags;
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} drm_sarea_drawable_t;
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typedef struct _dri_sarea_frame_t {
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unsigned int x;
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unsigned int y;
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unsigned int width;
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unsigned int height;
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unsigned int fullscreen;
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} drm_sarea_frame_t;
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typedef struct _drm_sarea_t {
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/* first thing is always the drm locking structure */
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drm_hw_lock_t lock;
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/* NOT_DONE: Use readers/writer lock for drawable_lock */
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drm_hw_lock_t drawable_lock;
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drm_sarea_drawable_t drawableTable[SAREA_MAX_DRAWABLES];
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drm_sarea_frame_t frame;
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drm_context_t dummy_context;
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} drm_sarea_t;
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#endif /* _DRM_SAREA_H_ */
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@ -355,6 +355,7 @@ typedef struct {
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int ctx_owner;
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int pfState; /* number of 3d windows (0,1,2ormore) */
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int pfCurrentPage; /* which buffer is being displayed? */
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int crtc2_base; /* CRTC2 frame offset */
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} drm_radeon_sarea_t;
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@ -109,8 +109,6 @@ typedef struct drm_radeon_private {
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int do_boxes;
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int page_flipping;
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int current_page;
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u32 crtc_offset;
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u32 crtc_offset_cntl;
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u32 color_fmt;
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unsigned int front_offset;
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@ -230,6 +228,8 @@ extern int radeon_emit_irq(drm_device_t *dev);
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#define RADEON_CRTC_OFFSET_CNTL 0x0228
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# define RADEON_CRTC_TILE_EN (1 << 15)
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# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
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#define RADEON_CRTC2_OFFSET 0x0324
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#define RADEON_CRTC2_OFFSET_CNTL 0x0328
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#define RADEON_RB3D_COLORPITCH 0x1c48
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|
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@ -30,6 +30,7 @@
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#include "radeon.h"
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#include "drmP.h"
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#include "drm.h"
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#include "drm_sarea.h"
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#include "radeon_drm.h"
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#include "radeon_drv.h"
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@ -803,6 +804,9 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev )
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static void radeon_cp_dispatch_flip( drm_device_t *dev )
|
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_sarea_t *sarea = (drm_sarea_t *)dev_priv->sarea->handle;
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int offset = (dev_priv->current_page == 1)
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? dev_priv->front_offset : dev_priv->back_offset;
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RING_LOCALS;
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DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n",
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__FUNCTION__,
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|
|
@ -816,18 +820,17 @@ static void radeon_cp_dispatch_flip( drm_device_t *dev )
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radeon_cp_performance_boxes( dev_priv );
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}
|
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|
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BEGIN_RING( 4 );
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/* Update the frame offsets for both CRTCs
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*/
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BEGIN_RING( 6 );
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|
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RADEON_WAIT_UNTIL_3D_IDLE();
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OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET, 0 ) );
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if ( dev_priv->current_page == 0 ) {
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OUT_RING( dev_priv->back_offset );
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dev_priv->current_page = 1;
|
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} else {
|
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OUT_RING( dev_priv->front_offset );
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dev_priv->current_page = 0;
|
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}
|
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OUT_RING_REG( RADEON_CRTC_OFFSET, ( ( sarea->frame.y * dev_priv->front_pitch
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+ sarea->frame.x
|
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* ( dev_priv->color_fmt - 2 ) ) & ~7 )
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+ offset );
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OUT_RING_REG( RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base
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+ offset );
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||||
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||||
ADVANCE_RING();
|
||||
|
||||
|
|
@ -836,7 +839,8 @@ static void radeon_cp_dispatch_flip( drm_device_t *dev )
|
|||
* performing the swapbuffer ioctl.
|
||||
*/
|
||||
dev_priv->sarea_priv->last_frame++;
|
||||
dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
|
||||
dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
|
||||
1 - dev_priv->current_page;
|
||||
|
||||
BEGIN_RING( 2 );
|
||||
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||||
|
|
@ -1304,12 +1308,12 @@ static int radeon_do_init_pageflip( drm_device_t *dev )
|
|||
|
||||
DRM_DEBUG( "\n" );
|
||||
|
||||
dev_priv->crtc_offset_cntl = RADEON_READ( RADEON_CRTC_OFFSET_CNTL );
|
||||
|
||||
BEGIN_RING( 4 );
|
||||
BEGIN_RING( 6 );
|
||||
RADEON_WAIT_UNTIL_3D_IDLE();
|
||||
OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET_CNTL, 0 ) );
|
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OUT_RING( dev_priv->crtc_offset_cntl | RADEON_CRTC_OFFSET_FLIP_CNTL );
|
||||
OUT_RING( RADEON_READ( RADEON_CRTC_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL );
|
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OUT_RING( CP_PACKET0( RADEON_CRTC2_OFFSET_CNTL, 0 ) );
|
||||
OUT_RING( RADEON_READ( RADEON_CRTC2_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL );
|
||||
ADVANCE_RING();
|
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|
||||
dev_priv->page_flipping = 1;
|
||||
|
|
@ -1330,10 +1334,6 @@ int radeon_do_cleanup_pageflip( drm_device_t *dev )
|
|||
if (dev_priv->current_page != 0)
|
||||
radeon_cp_dispatch_flip( dev );
|
||||
|
||||
/* FIXME: If the X server changes screen resolution, it
|
||||
* clobbers the value of RADEON_CRTC_OFFSET_CNTL, above,
|
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* leading to a flashing efect.
|
||||
*/
|
||||
dev_priv->page_flipping = 0;
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue