Merge branch 'r500-support'
Dave Airlie
commit
5e99b42b04
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@ -135,6 +135,101 @@
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0x1002 0x5e4c CHIP_RV410|RADEON_NEW_MEMMAP "ATI Radeon RV410 X700 SE"
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0x1002 0x5e4d CHIP_RV410|RADEON_NEW_MEMMAP "ATI Radeon RV410 X700"
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0x1002 0x5e4f CHIP_RV410|RADEON_NEW_MEMMAP "ATI Radeon RV410 X700 SE"
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0x1002 0x7100 CHIP_R520|RADEON_NEW_MEMMAP "ATI Radeon X1800"
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0x1002 0x7101 CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1800 XT"
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0x1002 0x7102 CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1800"
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0x1002 0x7103 CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility FireGL V7200"
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0x1002 0x7104 CHIP_R520|RADEON_NEW_MEMMAP "ATI FireGL V7200"
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0x1002 0x7105 CHIP_R520|RADEON_NEW_MEMMAP "ATI FireGL V5300"
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0x1002 0x7106 CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility FireGL V7100"
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0x1002 0x7108 CHIP_R520|RADEON_NEW_MEMMAP "ATI Radeon X1800"
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0x1002 0x7109 CHIP_R520|RADEON_NEW_MEMMAP "ATI Radeon X1800"
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0x1002 0x710A CHIP_R520|RADEON_NEW_MEMMAP "ATI Radeon X1800"
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0x1002 0x710B CHIP_R520|RADEON_NEW_MEMMAP "ATI Radeon X1800"
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0x1002 0x710C CHIP_R520|RADEON_NEW_MEMMAP "ATI Radeon X1800"
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0x1002 0x710E CHIP_R520|RADEON_NEW_MEMMAP "ATI FireGL V7300"
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0x1002 0x710F CHIP_R520|RADEON_NEW_MEMMAP "ATI FireGL V7350"
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0x1002 0x7140 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1600"
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0x1002 0x7141 CHIP_RV515|RADEON_NEW_MEMMAP "ATI RV505"
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0x1002 0x7142 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1300/X1550"
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0x1002 0x7143 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1550"
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0x1002 0x7144 CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI M54-GL"
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0x1002 0x7145 CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1400"
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0x1002 0x7146 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1300/X1550"
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0x1002 0x7147 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1550 64-bit"
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0x1002 0x7149 CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1300"
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0x1002 0x714A CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1300"
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0x1002 0x714B CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1300"
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0x1002 0x714C CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1300"
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0x1002 0x714D CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1300"
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0x1002 0x714E CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1300"
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0x1002 0x714F CHIP_RV515|RADEON_NEW_MEMMAP "ATI RV505"
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0x1002 0x7151 CHIP_RV515|RADEON_NEW_MEMMAP "ATI RV505"
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0x1002 0x7152 CHIP_RV515|RADEON_NEW_MEMMAP "ATI FireGL V3300"
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0x1002 0x7153 CHIP_RV515|RADEON_NEW_MEMMAP "ATI FireGL V3350"
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0x1002 0x715E CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1300"
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0x1002 0x715F CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1550 64-bit"
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0x1002 0x7180 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1300/X1550"
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0x1002 0x7181 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1600"
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0x1002 0x7183 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1300/X1550"
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0x1002 0x7186 CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1450"
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0x1002 0x7187 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1300/X1550"
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0x1002 0x7188 CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X2300"
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0x1002 0x718A CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X2300"
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0x1002 0x718B CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1350"
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0x1002 0x718C CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1350"
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0x1002 0x718D CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1450"
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0x1002 0x718F CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1300"
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0x1002 0x7193 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1550"
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0x1002 0x7196 CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1350"
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0x1002 0x719B CHIP_RV515|RADEON_NEW_MEMMAP "ATI FireMV 2250"
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0x1002 0x719F CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1550 64-bit"
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0x1002 0x71C0 CHIP_RV530|RADEON_NEW_MEMMAP "ATI Radeon X1600"
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0x1002 0x71C1 CHIP_RV530|RADEON_NEW_MEMMAP "ATI Radeon X1650"
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0x1002 0x71C2 CHIP_RV530|RADEON_NEW_MEMMAP "ATI Radeon X1600"
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0x1002 0x71C3 CHIP_RV530|RADEON_NEW_MEMMAP "ATI Radeon X1600"
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0x1002 0x71C4 CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility FireGL V5200"
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0x1002 0x71C5 CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1600"
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0x1002 0x71C6 CHIP_RV530|RADEON_NEW_MEMMAP "ATI Radeon X1650"
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0x1002 0x71C7 CHIP_RV530|RADEON_NEW_MEMMAP "ATI Radeon X1650"
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0x1002 0x71CD CHIP_RV530|RADEON_NEW_MEMMAP "ATI Radeon X1600"
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0x1002 0x71CE CHIP_RV530|RADEON_NEW_MEMMAP "ATI Radeon X1300 XT/X1600 Pro"
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0x1002 0x71D2 CHIP_RV530|RADEON_NEW_MEMMAP "ATI FireGL V3400"
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0x1002 0x71D4 CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility FireGL V5250"
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0x1002 0x71D5 CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1700"
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0x1002 0x71D6 CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1700 XT"
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0x1002 0x71DA CHIP_RV530|RADEON_NEW_MEMMAP "ATI FireGL V5200"
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0x1002 0x71DE CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1700"
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0x1002 0x7200 CHIP_RV530|RADEON_NEW_MEMMAP "ATI Radeon X2300HD"
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0x1002 0x7210 CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon HD 2300"
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0x1002 0x7211 CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon HD 2300"
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0x1002 0x7240 CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1950"
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0x1002 0x7243 CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900"
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0x1002 0x7244 CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1950"
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0x1002 0x7245 CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900"
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0x1002 0x7246 CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900"
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0x1002 0x7247 CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900"
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0x1002 0x7248 CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900"
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0x1002 0x7249 CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900"
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0x1002 0x724A CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900"
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0x1002 0x724B CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900"
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0x1002 0x724C CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900"
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0x1002 0x724D CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900"
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0x1002 0x724E CHIP_R580|RADEON_NEW_MEMMAP "ATI AMD Stream Processor"
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0x1002 0x724F CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900"
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0x1002 0x7280 CHIP_RV570|RADEON_NEW_MEMMAP "ATI Radeon X1950"
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0x1002 0x7281 CHIP_RV560|RADEON_NEW_MEMMAP "ATI RV560"
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0x1002 0x7283 CHIP_RV560|RADEON_NEW_MEMMAP "ATI RV560"
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0x1002 0x7284 CHIP_R580|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1900"
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0x1002 0x7287 CHIP_RV560|RADEON_NEW_MEMMAP "ATI RV560"
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0x1002 0x7288 CHIP_RV570|RADEON_NEW_MEMMAP "ATI Radeon X1950 GT"
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0x1002 0x7289 CHIP_RV570|RADEON_NEW_MEMMAP "ATI RV570"
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0x1002 0x728B CHIP_RV570|RADEON_NEW_MEMMAP "ATI RV570"
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0x1002 0x728C CHIP_RV570|RADEON_NEW_MEMMAP "ATI ATI FireGL V7400"
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0x1002 0x7290 CHIP_RV560|RADEON_NEW_MEMMAP "ATI RV560"
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0x1002 0x7291 CHIP_RV560|RADEON_NEW_MEMMAP "ATI Radeon X1650"
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0x1002 0x7293 CHIP_RV560|RADEON_NEW_MEMMAP "ATI Radeon X1650"
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0x1002 0x7297 CHIP_RV560|RADEON_NEW_MEMMAP "ATI RV560"
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0x1002 0x7834 CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP "ATI Radeon RS350 9000/9100 IGP"
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0x1002 0x7835 CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Radeon RS350 Mobility IGP"
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@ -77,23 +77,31 @@ static int r300_emit_cliprects(drm_radeon_private_t *dev_priv,
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return -EFAULT;
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}
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box.x1 =
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(box.x1 +
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R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
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box.y1 =
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(box.y1 +
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R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
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box.x2 =
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(box.x2 +
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R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
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box.y2 =
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(box.y2 +
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R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
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box.x1 = (box.x1) &
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R300_CLIPRECT_MASK;
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box.y1 = (box.y1) &
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R300_CLIPRECT_MASK;
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box.x2 = (box.x2) &
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R300_CLIPRECT_MASK;
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box.y2 = (box.y2) &
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R300_CLIPRECT_MASK;
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} else {
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box.x1 = (box.x1 + R300_CLIPRECT_OFFSET) &
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R300_CLIPRECT_MASK;
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box.y1 = (box.y1 + R300_CLIPRECT_OFFSET) &
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R300_CLIPRECT_MASK;
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box.x2 = (box.x2 + R300_CLIPRECT_OFFSET) &
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R300_CLIPRECT_MASK;
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box.y2 = (box.y2 + R300_CLIPRECT_OFFSET) &
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R300_CLIPRECT_MASK;
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}
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OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) |
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(box.y1 << R300_CLIPRECT_Y_SHIFT));
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OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) |
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(box.y2 << R300_CLIPRECT_Y_SHIFT));
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}
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OUT_RING_REG(R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr - 1]);
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@ -133,9 +141,11 @@ static int r300_emit_cliprects(drm_radeon_private_t *dev_priv,
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static u8 r300_reg_flags[0x10000 >> 2];
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void r300_init_reg_flags(void)
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void r300_init_reg_flags(struct drm_device *dev)
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{
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int i;
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drm_radeon_private_t *dev_priv = dev->dev_private;
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memset(r300_reg_flags, 0, 0x10000 >> 2);
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#define ADD_RANGE_MARK(reg, count,mark) \
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for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\
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@ -230,6 +240,9 @@ void r300_init_reg_flags(void)
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ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
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ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
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ADD_RANGE(0x4074, 16);
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}
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}
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static __inline__ int r300_check_range(unsigned reg, int count)
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@ -816,19 +816,44 @@ static const u32 R300_cp_microcode[][2] = {
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{ 0000000000, 0000000000 },
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};
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static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
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{
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u32 ret;
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RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
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ret = RADEON_READ(R520_MC_IND_DATA);
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RADEON_WRITE(R520_MC_IND_INDEX, 0);
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return ret;
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}
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u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
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{
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return RADEON_READ(RADEON_MC_FB_LOCATION);
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|
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
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return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
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return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
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else
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return RADEON_READ(RADEON_MC_FB_LOCATION);
|
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}
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|
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static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
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{
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RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
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RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
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RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
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else
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RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
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}
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static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
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{
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RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
|
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
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RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
|
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
|
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RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
|
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else
|
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RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
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}
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static int RADEON_READ_PLL(struct drm_device * dev, int addr)
|
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|
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@ -1089,41 +1114,43 @@ static int radeon_do_engine_reset(struct drm_device * dev)
|
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|
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radeon_do_pixcache_flush(dev_priv);
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|
||||
clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
|
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mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
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|
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RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
|
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RADEON_FORCEON_MCLKA |
|
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RADEON_FORCEON_MCLKB |
|
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RADEON_FORCEON_YCLKA |
|
||||
RADEON_FORCEON_YCLKB |
|
||||
RADEON_FORCEON_MC |
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RADEON_FORCEON_AIC));
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|
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rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
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|
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RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
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RADEON_SOFT_RESET_CP |
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RADEON_SOFT_RESET_HI |
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||||
RADEON_SOFT_RESET_SE |
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RADEON_SOFT_RESET_RE |
|
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RADEON_SOFT_RESET_PP |
|
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RADEON_SOFT_RESET_E2 |
|
||||
RADEON_SOFT_RESET_RB));
|
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RADEON_READ(RADEON_RBBM_SOFT_RESET);
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RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
|
||||
~(RADEON_SOFT_RESET_CP |
|
||||
RADEON_SOFT_RESET_HI |
|
||||
RADEON_SOFT_RESET_SE |
|
||||
RADEON_SOFT_RESET_RE |
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||||
RADEON_SOFT_RESET_PP |
|
||||
RADEON_SOFT_RESET_E2 |
|
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RADEON_SOFT_RESET_RB)));
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RADEON_READ(RADEON_RBBM_SOFT_RESET);
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||||
|
||||
RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
|
||||
RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
|
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RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
|
||||
clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
|
||||
mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
|
||||
|
||||
RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
|
||||
RADEON_FORCEON_MCLKA |
|
||||
RADEON_FORCEON_MCLKB |
|
||||
RADEON_FORCEON_YCLKA |
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||||
RADEON_FORCEON_YCLKB |
|
||||
RADEON_FORCEON_MC |
|
||||
RADEON_FORCEON_AIC));
|
||||
|
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rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
|
||||
|
||||
RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
|
||||
RADEON_SOFT_RESET_CP |
|
||||
RADEON_SOFT_RESET_HI |
|
||||
RADEON_SOFT_RESET_SE |
|
||||
RADEON_SOFT_RESET_RE |
|
||||
RADEON_SOFT_RESET_PP |
|
||||
RADEON_SOFT_RESET_E2 |
|
||||
RADEON_SOFT_RESET_RB));
|
||||
RADEON_READ(RADEON_RBBM_SOFT_RESET);
|
||||
RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
|
||||
~(RADEON_SOFT_RESET_CP |
|
||||
RADEON_SOFT_RESET_HI |
|
||||
RADEON_SOFT_RESET_SE |
|
||||
RADEON_SOFT_RESET_RE |
|
||||
RADEON_SOFT_RESET_PP |
|
||||
RADEON_SOFT_RESET_E2 |
|
||||
RADEON_SOFT_RESET_RB)));
|
||||
RADEON_READ(RADEON_RBBM_SOFT_RESET);
|
||||
|
||||
RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
|
||||
RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
|
||||
RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
|
||||
}
|
||||
|
||||
/* Reset the CP ring */
|
||||
radeon_do_cp_reset(dev_priv);
|
||||
|
|
@ -1859,7 +1886,7 @@ int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_pri
|
|||
LOCK_TEST_WITH_RETURN(dev, file_priv);
|
||||
|
||||
if (init->func == RADEON_INIT_R300_CP)
|
||||
r300_init_reg_flags();
|
||||
r300_init_reg_flags(dev);
|
||||
|
||||
switch (init->func) {
|
||||
case RADEON_INIT_CP:
|
||||
|
|
@ -2273,6 +2300,10 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
|
|||
case CHIP_R350:
|
||||
case CHIP_R420:
|
||||
case CHIP_RV410:
|
||||
case CHIP_RV515:
|
||||
case CHIP_R520:
|
||||
case CHIP_RV570:
|
||||
case CHIP_R580:
|
||||
dev_priv->flags |= RADEON_HAS_HIERZ;
|
||||
break;
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -124,6 +124,12 @@ enum radeon_family {
|
|||
CHIP_R420,
|
||||
CHIP_RV410,
|
||||
CHIP_RS400,
|
||||
CHIP_RV515,
|
||||
CHIP_R520,
|
||||
CHIP_RV530,
|
||||
CHIP_RV560,
|
||||
CHIP_RV570,
|
||||
CHIP_R580,
|
||||
CHIP_LAST,
|
||||
};
|
||||
|
||||
|
|
@ -391,7 +397,7 @@ extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
|
|||
unsigned long arg);
|
||||
|
||||
/* r300_cmdbuf.c */
|
||||
extern void r300_init_reg_flags(void);
|
||||
extern void r300_init_reg_flags(struct drm_device *dev);
|
||||
|
||||
extern int r300_do_cp_cmdbuf(struct drm_device *dev,
|
||||
struct drm_file *file_priv,
|
||||
|
|
@ -462,6 +468,15 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
|
|||
#define RADEON_IGPGART_ENABLE 0x38
|
||||
#define RADEON_IGPGART_UNK_39 0x39
|
||||
|
||||
#define R520_MC_IND_INDEX 0x70
|
||||
#define R520_MC_IND_WR_EN (1<<24)
|
||||
#define R520_MC_IND_DATA 0x74
|
||||
|
||||
#define RV515_MC_FB_LOCATION 0x01
|
||||
#define RV515_MC_AGP_LOCATION 0x02
|
||||
|
||||
#define R520_MC_FB_LOCATION 0x04
|
||||
#define R520_MC_AGP_LOCATION 0x05
|
||||
|
||||
#define RADEON_MPP_TB_CONFIG 0x01c0
|
||||
#define RADEON_MEM_CNTL 0x0140
|
||||
|
|
@ -1085,6 +1100,13 @@ do { \
|
|||
RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
|
||||
} while (0)
|
||||
|
||||
#define RADEON_WRITE_MCIND( addr, val ) \
|
||||
do { \
|
||||
RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
|
||||
RADEON_WRITE(R520_MC_IND_DATA, (val)); \
|
||||
RADEON_WRITE(R520_MC_IND_INDEX, 0); \
|
||||
} while (0)
|
||||
|
||||
#define CP_PACKET0( reg, n ) \
|
||||
(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
|
||||
#define CP_PACKET0_TABLE( reg, n ) \
|
||||
|
|
|
|||
Loading…
Reference in New Issue