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intel: Add some PCI IDs for Haswell. 

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
main
Kenneth Graunke 2012-03-19 13:55:19 -07:00
parent c50cc24690
commit 617213357e
1 changed files with 23 additions and 5 deletions
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28
intel/intel_chipset.h
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@ -45,6 +45,12 @@
#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
#define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */ #define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */
#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
#define PCI_CHIP_HASWELL_GT2 0x0412
#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
#define PCI_CHIP_HASWELL_M_GT2 0x0416
#define PCI_CHIP_HASWELL_M_ULT_GT2 0x0A16 /* Mobile ULT */
#define IS_830(dev) (dev == 0x3577) #define IS_830(dev) (dev == 0x3577)
#define IS_845(dev) (dev == 0x2562) #define IS_845(dev) (dev == 0x2562)
#define IS_85X(dev) (dev == 0x3582) #define IS_85X(dev) (dev == 0x3582)
@ -115,11 +121,23 @@
dev == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \ dev == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
dev == PCI_CHIP_SANDYBRIDGE_S) dev == PCI_CHIP_SANDYBRIDGE_S)
#define IS_GEN7(dev) (dev == PCI_CHIP_IVYBRIDGE_GT1 || \ #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
dev == PCI_CHIP_IVYBRIDGE_GT2 || \ IS_HASWELL(devid))
dev == PCI_CHIP_IVYBRIDGE_M_GT1 || \
dev == PCI_CHIP_IVYBRIDGE_M_GT2 || \ #define IS_IVYBRIDGE(dev) (dev == PCI_CHIP_IVYBRIDGE_GT1 || \
dev == PCI_CHIP_IVYBRIDGE_S) dev == PCI_CHIP_IVYBRIDGE_GT2 || \
dev == PCI_CHIP_IVYBRIDGE_M_GT1 || \
dev == PCI_CHIP_IVYBRIDGE_M_GT2 || \
dev == PCI_CHIP_IVYBRIDGE_S)
#define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \
devid == PCI_CHIP_HASWELL_M_GT1)
#define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2 || \
devid == PCI_CHIP_HASWELL_M_GT2 || \
devid == PCI_CHIP_HASWELL_M_ULT_GT2)
#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
IS_HSW_GT2(devid))
#define IS_G4X(dev) (dev == 0x2E02 || \ #define IS_G4X(dev) (dev == 0x2E02 || \
dev == 0x2E12 || \ dev == 0x2E12 || \