parent
14e3f2711e
commit
63c0f39460
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@ -1,4 +1,4 @@
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/ i915_dma.c -- DMA support for the I915 -*- linux-c -*-
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/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
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*/
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*/
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/*
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/*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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@ -31,11 +31,12 @@
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#include "i915_drm.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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#include "i915_drv.h"
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#define IS_I965G(dev) (dev->pdev->device == 0x2972 || \
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#define IS_I965G(dev) (dev->pci_device == 0x2972 || \
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dev->pdev->device == 0x2982 || \
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dev->pci_device == 0x2982 || \
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dev->pdev->device == 0x2992 || \
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dev->pci_device == 0x2992 || \
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dev->pdev->device == 0x29A2 || \
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dev->pci_device == 0x29A2 || \
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dev->pdev->device == 0x2A02)
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dev->pci_device == 0x2A02)
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/* Really want an OS-independent resettable timer. Would like to have
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/* Really want an OS-independent resettable timer. Would like to have
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* this loop run for (eg) 3 sec, but have the timer reset every time
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* this loop run for (eg) 3 sec, but have the timer reset every time
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@ -776,6 +777,61 @@ static int i915_setparam(DRM_IOCTL_ARGS)
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return 0;
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return 0;
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}
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}
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drm_i915_mmio_entry_t mmio_table[] = {
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[MMIO_REGS_PS_DEPTH_COUNT] = {
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I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
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0x2350,
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8
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}
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};
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static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
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static int i915_mmio(DRM_IOCTL_ARGS)
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{
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char buf[32];
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DRM_DEVICE;
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drm_i915_private_t *dev_priv = dev->dev_private;
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drm_i915_mmio_entry_t *e;
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drm_i915_mmio_t mmio;
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void __iomem *base;
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if (!dev_priv) {
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DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
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return DRM_ERR(EINVAL);
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}
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DRM_COPY_FROM_USER_IOCTL(mmio, (drm_i915_setparam_t __user *) data,
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sizeof(mmio));
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if (mmio.reg >= mmio_table_size)
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return DRM_ERR(EINVAL);
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e = &mmio_table[mmio.reg];
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base = dev_priv->mmio_map->handle + e->offset;
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switch (mmio.read_write) {
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case I915_MMIO_READ:
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if (!(e->flag & I915_MMIO_MAY_READ))
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return DRM_ERR(EINVAL);
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memcpy_fromio(buf, base, e->size);
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if (DRM_COPY_TO_USER(mmio.data, buf, e->size)) {
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DRM_ERROR("DRM_COPY_TO_USER failed\n");
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return DRM_ERR(EFAULT);
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}
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break;
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case I915_MMIO_WRITE:
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if (!(e->flag & I915_MMIO_MAY_WRITE))
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return DRM_ERR(EINVAL);
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if(DRM_COPY_FROM_USER(buf, mmio.data, e->size)) {
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DRM_ERROR("DRM_COPY_TO_USER failed\n");
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return DRM_ERR(EFAULT);
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}
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memcpy_toio(base, buf, e->size);
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break;
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}
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return 0;
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}
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int i915_driver_load(drm_device_t *dev, unsigned long flags)
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int i915_driver_load(drm_device_t *dev, unsigned long flags)
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{
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{
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/* i915 has 4 more counters */
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/* i915 has 4 more counters */
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@ -825,6 +881,7 @@ drm_ioctl_desc_t i915_ioctls[] = {
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[DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
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[DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
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[DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH },
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[DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH },
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[DRM_IOCTL_NR(DRM_I915_VBLANK_SWAP)] = {i915_vblank_swap, DRM_AUTH},
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[DRM_IOCTL_NR(DRM_I915_VBLANK_SWAP)] = {i915_vblank_swap, DRM_AUTH},
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[DRM_IOCTL_NR(DRM_I915_MMIO)] = {i915_mmio, DRM_AUTH},
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};
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};
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int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
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int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
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@ -152,6 +152,7 @@ typedef struct _drm_i915_sarea {
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#define DRM_I915_SET_VBLANK_PIPE 0x0d
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#define DRM_I915_SET_VBLANK_PIPE 0x0d
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#define DRM_I915_GET_VBLANK_PIPE 0x0e
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#define DRM_I915_GET_VBLANK_PIPE 0x0e
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#define DRM_I915_VBLANK_SWAP 0x0f
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#define DRM_I915_VBLANK_SWAP 0x0f
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#define DRM_I915_MMIO 0x10
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#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
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#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
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#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
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#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
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@ -170,7 +171,6 @@ typedef struct _drm_i915_sarea {
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#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
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#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
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#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
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#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
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/* Allow drivers to submit batchbuffers directly to hardware, relying
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/* Allow drivers to submit batchbuffers directly to hardware, relying
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* on the security mechanisms provided by hardware.
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* on the security mechanisms provided by hardware.
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*/
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*/
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@ -273,4 +273,32 @@ typedef struct drm_i915_vblank_swap {
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unsigned int sequence;
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unsigned int sequence;
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} drm_i915_vblank_swap_t;
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} drm_i915_vblank_swap_t;
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#define I915_MMIO_READ 0
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#define I915_MMIO_WRITE 1
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#define I915_MMIO_MAY_READ 0x1
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#define I915_MMIO_MAY_WRITE 0x2
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#define MMIO_REGS_IA_PRIMATIVES_COUNT 0
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#define MMIO_REGS_IA_VERTICES_COUNT 1
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#define MMIO_REGS_VS_INVOCATION_COUNT 2
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#define MMIO_REGS_GS_PRIMITIVES_COUNT 3
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#define MMIO_REGS_GS_INVOCATION_COUNT 4
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#define MMIO_REGS_CL_PRIMITIVES_COUNT 5
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#define MMIO_REGS_CL_INVOCATION_COUNT 6
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#define MMIO_REGS_PS_INVOCATION_COUNT 7
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#define MMIO_REGS_PS_DEPTH_COUNT 8
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typedef struct drm_i915_mmio_entry {
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unsigned int flag;
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unsigned int offset;
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unsigned int size;
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}drm_i915_mmio_entry_t;
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typedef struct drm_i915_mmio {
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unsigned int read_write:1;
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unsigned int reg:31;
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void __user *data;
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} drm_i915_mmio_t;
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#endif /* _I915_DRM_H_ */
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#endif /* _I915_DRM_H_ */
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