amdgpu: remove amdgpu_ib helpers
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>main
Marek Olšák
Alex Deucher
parent
194d5c2ee4
commit
646f5411cf
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@ -78,23 +78,6 @@ enum amdgpu_bo_handle_type {
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amdgpu_bo_handle_type_dma_buf_fd = 2
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};
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/**
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* For performance reasons and to simplify logic libdrm_amdgpu will handle
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* IBs only some pre-defined sizes.
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*
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* \sa amdgpu_cs_alloc_ib()
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*/
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enum amdgpu_cs_ib_size {
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amdgpu_cs_ib_size_4K = 0,
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amdgpu_cs_ib_size_16K = 1,
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amdgpu_cs_ib_size_32K = 2,
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amdgpu_cs_ib_size_64K = 3,
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amdgpu_cs_ib_size_128K = 4
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};
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/** The number of different IB sizes */
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#define AMDGPU_CS_IB_SIZE_NUM 5
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/*--------------------------------------------------------------------------*/
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/* -------------------------- Datatypes ----------------------------------- */
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@ -290,23 +273,6 @@ struct amdgpu_gds_alloc_info {
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uint32_t oa;
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};
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/**
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* Structure to described allocated command buffer (a.k.a. IB)
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*
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* \sa amdgpu_cs_alloc_ib()
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*
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*/
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struct amdgpu_cs_ib_alloc_result {
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/** IB allocation handle */
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amdgpu_bo_handle handle;
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/** Assigned GPU VM MC Address of command buffer */
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uint64_t mc_address;
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/** Address to be used for CPU access */
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void *cpu;
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};
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/**
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* Structure describing IB
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*
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@ -923,42 +889,6 @@ int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
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*
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*/
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/**
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* Allocate memory to be filled with PM4 packets and be served as the first
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* entry point of execution (a.k.a. Indirect Buffer)
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*
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* \param context - \c [in] GPU Context which will use IB
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* \param ib_size - \c [in] Size of allocation
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* \param output - \c [out] Pointer to structure to get information about
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* allocated IB
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*
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* \return 0 on success\n
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* >0 - AMD specific error code\n
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* <0 - Negative POSIX Error code
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*
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* \sa amdgpu_cs_free_ib()
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*
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*/
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int amdgpu_cs_alloc_ib(amdgpu_context_handle context,
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enum amdgpu_cs_ib_size ib_size,
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struct amdgpu_cs_ib_alloc_result *output);
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/**
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* If UMD has allocates IBs which doesn’t need any more than those IBs must
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* be explicitly freed
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*
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* \param handle - \c [in] IB handle
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*
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* \return 0 on success\n
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* >0 - AMD specific error code\n
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* <0 - Negative POSIX Error code
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*
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* \sa amdgpu_cs_alloc_ib()
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*
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*/
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int amdgpu_cs_free_ib(amdgpu_bo_handle handle);
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/**
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* Send request to submit command buffers to hardware.
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*
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@ -32,94 +32,6 @@
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#include "amdgpu_drm.h"
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#include "amdgpu_internal.h"
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/**
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* Create an IB buffer.
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*
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* \param dev - \c [in] Device handle
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* \param context - \c [in] GPU Context
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* \param ib_size - \c [in] Size of allocation
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* \param ib - \c [out] return the pointer to the created IB buffer
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*
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* \return 0 on success otherwise POSIX Error code
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*/
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int amdgpu_cs_alloc_ib(amdgpu_context_handle context,
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enum amdgpu_cs_ib_size ib_size,
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struct amdgpu_cs_ib_alloc_result *output)
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{
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struct amdgpu_bo_alloc_request alloc_buffer = {};
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struct amdgpu_bo_alloc_result info;
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int r;
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void *cpu;
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if (NULL == context)
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return -EINVAL;
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if (NULL == output)
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return -EINVAL;
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if (ib_size >= AMDGPU_CS_IB_SIZE_NUM)
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return -EINVAL;
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switch (ib_size) {
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case amdgpu_cs_ib_size_4K:
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alloc_buffer.alloc_size = 4 * 1024;
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break;
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case amdgpu_cs_ib_size_16K:
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alloc_buffer.alloc_size = 16 * 1024;
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break;
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case amdgpu_cs_ib_size_32K:
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alloc_buffer.alloc_size = 32 * 1024;
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break;
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case amdgpu_cs_ib_size_64K:
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alloc_buffer.alloc_size = 64 * 1024;
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break;
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case amdgpu_cs_ib_size_128K:
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alloc_buffer.alloc_size = 128 * 1024;
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break;
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default:
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return -EINVAL;
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}
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alloc_buffer.phys_alignment = 4 * 1024;
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alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
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r = amdgpu_bo_alloc(context->dev,
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&alloc_buffer,
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&info);
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if (r)
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return r;
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r = amdgpu_bo_cpu_map(info.buf_handle, &cpu);
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if (r) {
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amdgpu_bo_free(info.buf_handle);
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return r;
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}
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output->handle = info.buf_handle;
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output->cpu = cpu;
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output->mc_address = info.virtual_mc_base_address;
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return 0;
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}
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/**
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* Destroy an IB buffer.
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*
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* \param ib - \c [in] IB handle
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*
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* \return 0 on success otherwise POSIX Error code
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*/
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int amdgpu_cs_free_ib(amdgpu_bo_handle bo)
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{
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int r;
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if (!bo)
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return -EINVAL;
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r = amdgpu_bo_cpu_unmap(bo);
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if (r)
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return r;
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return amdgpu_bo_free(bo);
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}
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/**
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* Create command submission context
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*
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@ -131,4 +131,33 @@ static inline amdgpu_bo_handle gpu_mem_alloc(
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return res.buf_handle;
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}
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static inline int
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amdgpu_bo_alloc_and_map(amdgpu_device_handle dev, unsigned size,
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unsigned alignment, unsigned heap, uint64_t flags,
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amdgpu_bo_handle *bo, void **cpu, uint64_t *mc_address)
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{
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struct amdgpu_bo_alloc_request request = {};
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struct amdgpu_bo_alloc_result out;
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int r;
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request.alloc_size = size;
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request.phys_alignment = alignment;
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request.preferred_heap = heap;
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request.flags = flags;
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r = amdgpu_bo_alloc(dev, &request, &out);
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if (r)
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return r;
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r = amdgpu_bo_cpu_map(out.buf_handle, cpu);
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if (r) {
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amdgpu_bo_free(out.buf_handle);
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return r;
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}
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*bo = out.buf_handle;
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*mc_address = out.virtual_mc_base_address;
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return 0;
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}
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#endif /* #ifdef _AMDGPU_TEST_H_ */
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@ -156,8 +156,9 @@ static void amdgpu_memory_alloc(void)
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static void amdgpu_command_submission_gfx_separate_ibs(void)
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{
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amdgpu_context_handle context_handle;
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struct amdgpu_cs_ib_alloc_result ib_result = {0};
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struct amdgpu_cs_ib_alloc_result ib_result_ce = {0};
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amdgpu_bo_handle ib_result_handle, ib_result_ce_handle;
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void *ib_result_cpu, *ib_result_ce_cpu;
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uint64_t ib_result_mc_address, ib_result_ce_mc_address;
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struct amdgpu_cs_request ibs_request = {0};
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struct amdgpu_cs_ib_info ib_info[2];
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struct amdgpu_cs_query_fence fence_status = {0};
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@ -168,31 +169,35 @@ static void amdgpu_command_submission_gfx_separate_ibs(void)
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r = amdgpu_cs_ctx_create(device_handle, &context_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_cs_alloc_ib(context_handle,
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amdgpu_cs_ib_size_4K, &ib_result);
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r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
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AMDGPU_GEM_DOMAIN_GTT, 0,
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&ib_result_handle, &ib_result_cpu,
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&ib_result_mc_address);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_cs_alloc_ib(context_handle,
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amdgpu_cs_ib_size_4K, &ib_result_ce);
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r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
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AMDGPU_GEM_DOMAIN_GTT, 0,
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&ib_result_ce_handle, &ib_result_ce_cpu,
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&ib_result_ce_mc_address);
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CU_ASSERT_EQUAL(r, 0);
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memset(ib_info, 0, 2 * sizeof(struct amdgpu_cs_ib_info));
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/* IT_SET_CE_DE_COUNTERS */
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ptr = ib_result_ce.cpu;
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ptr = ib_result_ce_cpu;
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ptr[0] = 0xc0008900;
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ptr[1] = 0;
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ptr[2] = 0xc0008400;
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ptr[3] = 1;
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ib_info[0].bo_handle = ib_result_ce.handle;
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ib_info[0].bo_handle = ib_result_ce_handle;
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ib_info[0].size = 4;
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ib_info[0].flags = AMDGPU_IB_FLAG_CE;
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/* IT_WAIT_ON_CE_COUNTER */
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ptr = ib_result.cpu;
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ptr = ib_result_cpu;
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ptr[0] = 0xc0008600;
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ptr[1] = 0x00000001;
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ib_info[1].bo_handle = ib_result.handle;
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ib_info[1].bo_handle = ib_result_handle;
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ib_info[1].size = 2;
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ibs_request.ip_type = AMDGPU_HW_IP_GFX;
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@ -210,10 +215,10 @@ static void amdgpu_command_submission_gfx_separate_ibs(void)
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r = amdgpu_cs_query_fence_status(&fence_status, &expired);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_cs_free_ib(ib_result.handle);
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r = amdgpu_bo_free(ib_result_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_cs_free_ib(ib_result_ce.handle);
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r = amdgpu_bo_free(ib_result_ce_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_cs_ctx_free(context_handle);
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@ -223,7 +228,9 @@ static void amdgpu_command_submission_gfx_separate_ibs(void)
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static void amdgpu_command_submission_gfx_shared_ib(void)
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{
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amdgpu_context_handle context_handle;
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struct amdgpu_cs_ib_alloc_result ib_result = {0};
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amdgpu_bo_handle ib_result_handle;
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void *ib_result_cpu;
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uint64_t ib_result_mc_address;
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struct amdgpu_cs_request ibs_request = {0};
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struct amdgpu_cs_ib_info ib_info[2];
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struct amdgpu_cs_query_fence fence_status = {0};
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@ -234,26 +241,28 @@ static void amdgpu_command_submission_gfx_shared_ib(void)
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r = amdgpu_cs_ctx_create(device_handle, &context_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_cs_alloc_ib(context_handle,
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amdgpu_cs_ib_size_4K, &ib_result);
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r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
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AMDGPU_GEM_DOMAIN_GTT, 0,
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&ib_result_handle, &ib_result_cpu,
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&ib_result_mc_address);
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CU_ASSERT_EQUAL(r, 0);
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memset(ib_info, 0, 2 * sizeof(struct amdgpu_cs_ib_info));
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/* IT_SET_CE_DE_COUNTERS */
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ptr = ib_result.cpu;
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ptr = ib_result_cpu;
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ptr[0] = 0xc0008900;
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ptr[1] = 0;
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ptr[2] = 0xc0008400;
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ptr[3] = 1;
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ib_info[0].bo_handle = ib_result.handle;
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ib_info[0].bo_handle = ib_result_handle;
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ib_info[0].size = 4;
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ib_info[0].flags = AMDGPU_IB_FLAG_CE;
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ptr = (uint32_t *)ib_result.cpu + 4;
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ptr = (uint32_t *)ib_result_cpu + 4;
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ptr[0] = 0xc0008600;
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ptr[1] = 0x00000001;
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ib_info[1].bo_handle = ib_result.handle;
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ib_info[1].bo_handle = ib_result_handle;
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ib_info[1].size = 2;
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ib_info[1].offset_dw = 4;
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@ -272,7 +281,7 @@ static void amdgpu_command_submission_gfx_shared_ib(void)
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r = amdgpu_cs_query_fence_status(&fence_status, &expired);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_cs_free_ib(ib_result.handle);
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r = amdgpu_bo_free(ib_result_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_cs_ctx_free(context_handle);
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@ -290,7 +299,9 @@ static void amdgpu_command_submission_gfx(void)
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static void amdgpu_command_submission_compute(void)
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{
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amdgpu_context_handle context_handle;
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struct amdgpu_cs_ib_alloc_result ib_result;
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amdgpu_bo_handle ib_result_handle;
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void *ib_result_cpu;
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uint64_t ib_result_mc_address;
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struct amdgpu_cs_request ibs_request;
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struct amdgpu_cs_ib_info ib_info;
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struct amdgpu_cs_query_fence fence_status;
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@ -302,17 +313,18 @@ static void amdgpu_command_submission_compute(void)
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CU_ASSERT_EQUAL(r, 0);
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for (instance = 0; instance < 8; instance++) {
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memset(&ib_result, 0, sizeof(struct amdgpu_cs_ib_alloc_result));
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r = amdgpu_cs_alloc_ib(context_handle,
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amdgpu_cs_ib_size_4K, &ib_result);
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r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
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AMDGPU_GEM_DOMAIN_GTT, 0,
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&ib_result_handle, &ib_result_cpu,
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&ib_result_mc_address);
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CU_ASSERT_EQUAL(r, 0);
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ptr = ib_result.cpu;
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ptr = ib_result_cpu;
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for (i = 0; i < 16; ++i)
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ptr[i] = 0xffff1000;
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memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
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ib_info.bo_handle = ib_result.handle;
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ib_info.bo_handle = ib_result_handle;
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ib_info.size = 16;
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memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
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@ -334,7 +346,7 @@ static void amdgpu_command_submission_compute(void)
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r = amdgpu_cs_query_fence_status(&fence_status, &expired);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_cs_free_ib(ib_result.handle);
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r = amdgpu_bo_free(ib_result_handle);
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CU_ASSERT_EQUAL(r, 0);
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}
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@ -356,7 +368,9 @@ static void amdgpu_sdma_test_exec_cs(amdgpu_context_handle context_handle,
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int r, i, j;
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uint32_t expired;
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uint32_t *ring_ptr;
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struct amdgpu_cs_ib_alloc_result ib_result = {0};
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amdgpu_bo_handle ib_result_handle;
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void *ib_result_cpu;
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uint64_t ib_result_mc_address;
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struct amdgpu_cs_query_fence fence_status = {0};
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/* prepare CS */
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@ -367,15 +381,17 @@ static void amdgpu_sdma_test_exec_cs(amdgpu_context_handle context_handle,
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CU_ASSERT_TRUE(pm4_dw <= 1024);
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/* allocate IB */
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r = amdgpu_cs_alloc_ib(context_handle,
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amdgpu_cs_ib_size_4K, &ib_result);
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r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
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AMDGPU_GEM_DOMAIN_GTT, 0,
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&ib_result_handle, &ib_result_cpu,
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&ib_result_mc_address);
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CU_ASSERT_EQUAL(r, 0);
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/* copy PM4 packet to ring from caller */
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ring_ptr = ib_result.cpu;
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ring_ptr = ib_result_cpu;
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memcpy(ring_ptr, pm4_src, pm4_dw * sizeof(*pm4_src));
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ib_info->bo_handle = ib_result.handle;
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ib_info->bo_handle = ib_result_handle;
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ib_info->size = pm4_dw;
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ibs_request->ip_type = AMDGPU_HW_IP_DMA;
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@ -407,7 +423,7 @@ static void amdgpu_sdma_test_exec_cs(amdgpu_context_handle context_handle,
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CU_ASSERT_EQUAL(r, 0);
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CU_ASSERT_EQUAL(expired, true);
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r = amdgpu_cs_free_ib(ib_result.handle);
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r = amdgpu_bo_free(ib_result_handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
#include "amdgpu_drm.h"
|
||||
#include "amdgpu_internal.h"
|
||||
|
||||
#define IB_SIZE amdgpu_cs_ib_size_4K
|
||||
#define IB_SIZE 4096
|
||||
#define MAX_RESOURCES 16
|
||||
|
||||
static amdgpu_device_handle device_handle;
|
||||
|
|
@ -59,7 +59,9 @@ CU_TestInfo cs_tests[] = {
|
|||
|
||||
int suite_cs_tests_init(void)
|
||||
{
|
||||
struct amdgpu_cs_ib_alloc_result ib_result = {0};
|
||||
amdgpu_bo_handle ib_result_handle;
|
||||
void *ib_result_cpu;
|
||||
uint64_t ib_result_mc_address;
|
||||
int r;
|
||||
|
||||
r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
|
||||
|
|
@ -73,12 +75,15 @@ int suite_cs_tests_init(void)
|
|||
if (r)
|
||||
return CUE_SINIT_FAILED;
|
||||
|
||||
r = amdgpu_cs_alloc_ib(context_handle, IB_SIZE, &ib_result);
|
||||
r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
|
||||
AMDGPU_GEM_DOMAIN_GTT, 0,
|
||||
&ib_result_handle, &ib_result_cpu,
|
||||
&ib_result_mc_address);
|
||||
if (r)
|
||||
return CUE_SINIT_FAILED;
|
||||
|
||||
ib_handle = ib_result.handle;
|
||||
ib_cpu = ib_result.cpu;
|
||||
ib_handle = ib_result_handle;
|
||||
ib_cpu = ib_result_cpu;
|
||||
|
||||
return CUE_SUCCESS;
|
||||
}
|
||||
|
|
@ -87,7 +92,7 @@ int suite_cs_tests_clean(void)
|
|||
{
|
||||
int r;
|
||||
|
||||
r = amdgpu_cs_free_ib(ib_handle);
|
||||
r = amdgpu_bo_free(ib_handle);
|
||||
if (r)
|
||||
return CUE_SCLEAN_FAILED;
|
||||
|
||||
|
|
@ -104,7 +109,6 @@ int suite_cs_tests_clean(void)
|
|||
|
||||
static int submit(unsigned ndw, unsigned ip)
|
||||
{
|
||||
struct amdgpu_cs_ib_alloc_result ib_result = {0};
|
||||
struct amdgpu_cs_request ibs_request = {0};
|
||||
struct amdgpu_cs_ib_info ib_info = {0};
|
||||
struct amdgpu_cs_query_fence fence_status = {0};
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@
|
|||
#include "vce_ib.h"
|
||||
#include "frame.h"
|
||||
|
||||
#define IB_SIZE amdgpu_cs_ib_size_4K
|
||||
#define IB_SIZE 4096
|
||||
#define MAX_RESOURCES 16
|
||||
|
||||
struct amdgpu_vce_bo {
|
||||
|
|
@ -64,9 +64,9 @@ static amdgpu_context_handle context_handle;
|
|||
static amdgpu_bo_handle ib_handle;
|
||||
uint32_t *ib_cpu;
|
||||
|
||||
struct amdgpu_vce_encode enc;
|
||||
amdgpu_bo_handle resources[MAX_RESOURCES];
|
||||
unsigned num_resources;
|
||||
static struct amdgpu_vce_encode enc;
|
||||
static amdgpu_bo_handle resources[MAX_RESOURCES];
|
||||
static unsigned num_resources;
|
||||
|
||||
static void amdgpu_cs_vce_create(void);
|
||||
static void amdgpu_cs_vce_encode(void);
|
||||
|
|
@ -81,7 +81,6 @@ CU_TestInfo vce_tests[] = {
|
|||
|
||||
int suite_vce_tests_init(void)
|
||||
{
|
||||
struct amdgpu_cs_ib_alloc_result ib_result = {0};
|
||||
int r;
|
||||
|
||||
r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
|
||||
|
|
@ -95,13 +94,13 @@ int suite_vce_tests_init(void)
|
|||
if (r)
|
||||
return CUE_SINIT_FAILED;
|
||||
|
||||
r = amdgpu_cs_alloc_ib(context_handle, IB_SIZE, &ib_result);
|
||||
r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
|
||||
AMDGPU_GEM_DOMAIN_GTT, 0,
|
||||
&ib_handle, (void**)&ib_cpu,
|
||||
&ib_mc_address);
|
||||
if (r)
|
||||
return CUE_SINIT_FAILED;
|
||||
|
||||
ib_handle = ib_result.handle;
|
||||
ib_cpu = ib_result.cpu;
|
||||
|
||||
memset(&enc, 0, sizeof(struct amdgpu_vce_encode));
|
||||
|
||||
return CUE_SUCCESS;
|
||||
|
|
@ -111,7 +110,7 @@ int suite_vce_tests_clean(void)
|
|||
{
|
||||
int r;
|
||||
|
||||
r = amdgpu_cs_free_ib(ib_handle);
|
||||
r = amdgpu_bo_free(ib_handle);
|
||||
if (r)
|
||||
return CUE_SCLEAN_FAILED;
|
||||
|
||||
|
|
@ -128,7 +127,6 @@ int suite_vce_tests_clean(void)
|
|||
|
||||
static int submit(unsigned ndw, unsigned ip)
|
||||
{
|
||||
struct amdgpu_cs_ib_alloc_result ib_result = {0};
|
||||
struct amdgpu_cs_request ibs_request = {0};
|
||||
struct amdgpu_cs_ib_info ib_info = {0};
|
||||
struct amdgpu_cs_query_fence fence_status = {0};
|
||||
|
|
@ -157,13 +155,13 @@ static int submit(unsigned ndw, unsigned ip)
|
|||
if (r)
|
||||
return r;
|
||||
|
||||
r = amdgpu_cs_alloc_ib(context_handle, IB_SIZE, &ib_result);
|
||||
r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
|
||||
AMDGPU_GEM_DOMAIN_GTT, 0,
|
||||
&ib_handle, (void**)&ib_cpu,
|
||||
&ib_mc_address);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
ib_handle = ib_result.handle;
|
||||
ib_cpu = ib_result.cpu;
|
||||
|
||||
fence_status.context = context_handle;
|
||||
fence_status.timeout_ns = AMDGPU_TIMEOUT_INFINITE;
|
||||
fence_status.ip_type = ip;
|
||||
|
|
@ -374,7 +372,6 @@ static void amdgpu_cs_vce_encode(void)
|
|||
|
||||
vbuf_size = enc.width * enc.height * 1.5;
|
||||
cpb_size = vbuf_size * 10;
|
||||
|
||||
num_resources = 0;
|
||||
alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
|
||||
resources[num_resources++] = enc.fb[0].handle;
|
||||
|
|
|
|||
Loading…
Reference in New Issue