Eliminate several useless ioctls and associated cruft.
The ioctlss XGI_ESC_DEVICE_INFO, XGI_ESC_MEM_COLLECT, XGI_ESC_PCIE_CHECK, XGI_ESC_GET_SCREEN_INFO, XGI_ESC_PUT_SCREEN_INFO, XGI_ESC_MMIO_INFO, and XGI_ESC_SAREA_INFO, are completely unnecessary. The will be doubly useless when the driver is converted to the DRM infrastructure.main
parent
4575d5b8f1
commit
658ff2daf3
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@ -877,10 +877,6 @@ int xgi_kern_ioctl(struct inode *inode, struct file *filp,
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arg_size);
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switch (_IOC_NR(cmd)) {
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case XGI_ESC_DEVICE_INFO:
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XGI_INFO("Jong-xgi_ioctl_get_device_info \n");
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xgi_get_device_info(info, (struct xgi_chip_info *)arg_copy);
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break;
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case XGI_ESC_POST_VBIOS:
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XGI_INFO("Jong-xgi_ioctl_post_vbios \n");
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break;
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@ -892,10 +888,6 @@ int xgi_kern_ioctl(struct inode *inode, struct file *filp,
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XGI_INFO("Jong-xgi_ioctl_fb_free \n");
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xgi_fb_free(info, *(unsigned long *)arg_copy);
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break;
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case XGI_ESC_MEM_COLLECT:
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XGI_INFO("Jong-xgi_ioctl_mem_collect \n");
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xgi_mem_collect(info, (unsigned int *)arg_copy);
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break;
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case XGI_ESC_PCIE_ALLOC:
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XGI_INFO("Jong-xgi_ioctl_pcie_alloc \n");
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xgi_pcie_alloc(info, alloc, 0);
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@ -905,30 +897,10 @@ int xgi_kern_ioctl(struct inode *inode, struct file *filp,
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*((unsigned long *)arg_copy));
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xgi_pcie_free(info, *((unsigned long *)arg_copy));
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break;
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case XGI_ESC_PCIE_CHECK:
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XGI_INFO("Jong-xgi_pcie_heap_check \n");
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xgi_pcie_heap_check();
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break;
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case XGI_ESC_GET_SCREEN_INFO:
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XGI_INFO("Jong-xgi_get_screen_info \n");
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xgi_get_screen_info(info, (struct xgi_screen_info *)arg_copy);
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break;
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case XGI_ESC_PUT_SCREEN_INFO:
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XGI_INFO("Jong-xgi_put_screen_info \n");
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xgi_put_screen_info(info, (struct xgi_screen_info *)arg_copy);
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break;
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case XGI_ESC_MMIO_INFO:
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XGI_INFO("Jong-xgi_ioctl_get_mmio_info \n");
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xgi_get_mmio_info(info, (struct xgi_mmio_info *)arg_copy);
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break;
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case XGI_ESC_GE_RESET:
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XGI_INFO("Jong-xgi_ioctl_ge_reset \n");
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xgi_ge_reset(info);
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break;
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case XGI_ESC_SAREA_INFO:
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XGI_INFO("Jong-xgi_ioctl_sarea_info \n");
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xgi_sarea_info(info, (struct xgi_sarea_info *)arg_copy);
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break;
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case XGI_ESC_DUMP_REGISTER:
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XGI_INFO("Jong-xgi_ioctl_dump_register \n");
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xgi_dump_register(info);
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@ -110,8 +110,6 @@ struct xgi_info {
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struct xgi_aperture mmio;
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struct xgi_aperture fb;
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struct xgi_aperture pcie;
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struct xgi_screen_info scrn_info;
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struct xgi_sarea_info sarea_info;
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/* look up table parameters */
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u32 *lut_base;
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@ -207,7 +205,6 @@ extern void xgi_pcie_heap_cleanup(struct xgi_info * info);
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extern void xgi_pcie_alloc(struct xgi_info * info,
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struct xgi_mem_alloc * alloc, pid_t pid);
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extern void xgi_pcie_free(struct xgi_info * info, unsigned long offset);
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extern void xgi_pcie_heap_check(void);
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extern struct xgi_pcie_block *xgi_find_pcie_block(struct xgi_info * info,
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unsigned long address);
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extern void *xgi_find_pcie_virt(struct xgi_info * info, unsigned long address);
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@ -31,78 +31,12 @@
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#include "xgi_regs.h"
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#include "xgi_pcie.h"
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void xgi_get_device_info(struct xgi_info * info, struct xgi_chip_info * req)
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{
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req->device_id = info->dev->device;
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req->device_name[0] = 'x';
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req->device_name[1] = 'g';
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req->device_name[2] = '4';
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req->device_name[3] = '7';
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req->vendor_id = info->dev->vendor;
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req->curr_display_mode = 0;
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req->fb_size = info->fb.size;
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req->sarea_bus_addr = info->sarea_info.bus_addr;
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req->sarea_size = info->sarea_info.size;
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}
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void xgi_get_mmio_info(struct xgi_info * info, struct xgi_mmio_info * req)
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{
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req->mmio_base = info->mmio.base;
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req->size = info->mmio.size;
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}
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void xgi_put_screen_info(struct xgi_info * info, struct xgi_screen_info * req)
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{
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info->scrn_info.scrn_start = req->scrn_start;
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info->scrn_info.scrn_xres = req->scrn_xres;
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info->scrn_info.scrn_yres = req->scrn_yres;
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info->scrn_info.scrn_bpp = req->scrn_bpp;
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info->scrn_info.scrn_pitch = req->scrn_pitch;
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XGI_INFO("info->scrn_info.scrn_start: 0x%lx"
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"info->scrn_info.scrn_xres: 0x%lx"
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"info->scrn_info.scrn_yres: 0x%lx"
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"info->scrn_info.scrn_bpp: 0x%lx"
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"info->scrn_info.scrn_pitch: 0x%lx\n",
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info->scrn_info.scrn_start,
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info->scrn_info.scrn_xres,
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info->scrn_info.scrn_yres,
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info->scrn_info.scrn_bpp, info->scrn_info.scrn_pitch);
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}
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void xgi_get_screen_info(struct xgi_info * info, struct xgi_screen_info * req)
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{
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req->scrn_start = info->scrn_info.scrn_start;
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req->scrn_xres = info->scrn_info.scrn_xres;
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req->scrn_yres = info->scrn_info.scrn_yres;
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req->scrn_bpp = info->scrn_info.scrn_bpp;
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req->scrn_pitch = info->scrn_info.scrn_pitch;
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XGI_INFO("req->scrn_start: 0x%lx"
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"req->scrn_xres: 0x%lx"
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"req->scrn_yres: 0x%lx"
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"req->scrn_bpp: 0x%lx"
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"req->scrn_pitch: 0x%lx\n",
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req->scrn_start,
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req->scrn_xres,
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req->scrn_yres, req->scrn_bpp, req->scrn_pitch);
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}
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void xgi_ge_reset(struct xgi_info * info)
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{
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xgi_disable_ge(info);
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xgi_enable_ge(info);
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}
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void xgi_sarea_info(struct xgi_info * info, struct xgi_sarea_info * req)
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{
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info->sarea_info.bus_addr = req->bus_addr;
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info->sarea_info.size = req->size;
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XGI_INFO("info->sarea_info.bus_addr: 0x%lx"
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"info->sarea_info.size: 0x%lx\n",
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info->sarea_info.bus_addr, info->sarea_info.size);
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}
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/*
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* irq functions
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*/
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@ -30,12 +30,7 @@
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#define _XGI_MISC_H_
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extern void xgi_dump_register(struct xgi_info * info);
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extern void xgi_get_device_info(struct xgi_info * info, struct xgi_chip_info * req);
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extern void xgi_get_mmio_info(struct xgi_info * info, struct xgi_mmio_info * req);
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extern void xgi_get_screen_info(struct xgi_info * info, struct xgi_screen_info * req);
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extern void xgi_put_screen_info(struct xgi_info * info, struct xgi_screen_info * req);
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extern void xgi_ge_reset(struct xgi_info * info);
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extern void xgi_sarea_info(struct xgi_info * info, struct xgi_sarea_info * req);
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extern void xgi_restore_registers(struct xgi_info * info);
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extern bool xgi_ge_irq_handler(struct xgi_info * info);
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@ -344,35 +344,6 @@ int xgi_pcie_heap_init(struct xgi_info * info)
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return 0;
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}
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void xgi_pcie_heap_check(void)
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{
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#ifdef XGI_DEBUG
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struct xgi_pcie_block *block;
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unsigned int ownerIndex;
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static const char *const ownerStr[6] =
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{ "2D", "3D", "3D_CMD", "3D_SCR", "3D_TEX", "ELSE" };
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if (!xgi_pcie_heap) {
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return;
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}
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XGI_INFO("pcie freemax = 0x%lx\n", xgi_pcie_heap->max_freesize);
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list_for_each_entry(block, &xgi_pcie_heap->used_list, list) {
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if (block->owner == PCIE_2D)
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ownerIndex = 0;
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else if (block->owner > PCIE_3D_TEXTURE
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|| block->owner < PCIE_2D
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|| block->owner < PCIE_3D)
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ownerIndex = 5;
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else
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ownerIndex = block->owner - PCIE_3D + 1;
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XGI_INFO("Allocated by %s, block offset: 0x%lx, size: 0x%lx \n",
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ownerStr[ownerIndex], block->offset, block->size);
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}
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#endif
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}
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void xgi_pcie_heap_cleanup(struct xgi_info * info)
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{
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struct list_head *free_list;
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@ -31,15 +31,17 @@
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#include <linux/types.h>
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#include <asm/ioctl.h>
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struct xgi_chip_info {
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struct drm_xgi_sarea {
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__u16 device_id;
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__u16 vendor_id;
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char device_name[32];
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unsigned int curr_display_mode; //Singe, DualView(Contained), MHS
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unsigned int fb_size;
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unsigned long sarea_bus_addr;
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unsigned int sarea_size;
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unsigned int scrn_start;
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unsigned int scrn_xres;
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unsigned int scrn_yres;
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unsigned int scrn_bpp;
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unsigned int scrn_pitch;
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};
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enum xgi_mem_location {
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unsigned long bus_addr;
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};
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struct xgi_screen_info {
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unsigned int scrn_start;
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unsigned int scrn_xres;
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unsigned int scrn_yres;
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unsigned int scrn_bpp;
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unsigned int scrn_pitch;
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};
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struct xgi_sarea_info {
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unsigned long bus_addr;
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unsigned int size;
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#define XGI_IOCTL_MAGIC 'x' /* use 'x' as magic number */
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#define XGI_IOCTL_BASE 0
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#define XGI_ESC_DEVICE_INFO (XGI_IOCTL_BASE + 0)
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#define XGI_ESC_POST_VBIOS (XGI_IOCTL_BASE + 1)
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#define XGI_ESC_POST_VBIOS (XGI_IOCTL_BASE + 0)
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#define XGI_ESC_FB_INIT (XGI_IOCTL_BASE + 2)
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#define XGI_ESC_FB_ALLOC (XGI_IOCTL_BASE + 3)
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#define XGI_ESC_FB_FREE (XGI_IOCTL_BASE + 4)
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#define XGI_ESC_PCIE_INIT (XGI_IOCTL_BASE + 5)
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#define XGI_ESC_PCIE_ALLOC (XGI_IOCTL_BASE + 6)
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#define XGI_ESC_PCIE_FREE (XGI_IOCTL_BASE + 7)
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#define XGI_ESC_SUBMIT_CMDLIST (XGI_IOCTL_BASE + 8)
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#define XGI_ESC_PUT_SCREEN_INFO (XGI_IOCTL_BASE + 9)
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#define XGI_ESC_GET_SCREEN_INFO (XGI_IOCTL_BASE + 10)
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#define XGI_ESC_GE_RESET (XGI_IOCTL_BASE + 11)
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#define XGI_ESC_SAREA_INFO (XGI_IOCTL_BASE + 12)
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#define XGI_ESC_DUMP_REGISTER (XGI_IOCTL_BASE + 13)
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#define XGI_ESC_DEBUG_INFO (XGI_IOCTL_BASE + 14)
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#define XGI_ESC_TEST_RWINKERNEL (XGI_IOCTL_BASE + 16)
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#define XGI_ESC_STATE_CHANGE (XGI_IOCTL_BASE + 17)
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#define XGI_ESC_MMIO_INFO (XGI_IOCTL_BASE + 18)
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#define XGI_ESC_PCIE_CHECK (XGI_IOCTL_BASE + 19)
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#define XGI_ESC_MEM_COLLECT (XGI_IOCTL_BASE + 20)
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#define XGI_ESC_FB_ALLOC (XGI_IOCTL_BASE + 1)
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#define XGI_ESC_FB_FREE (XGI_IOCTL_BASE + 2)
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#define XGI_ESC_PCIE_ALLOC (XGI_IOCTL_BASE + 3)
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#define XGI_ESC_PCIE_FREE (XGI_IOCTL_BASE + 4)
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#define XGI_ESC_SUBMIT_CMDLIST (XGI_IOCTL_BASE + 5)
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#define XGI_ESC_GE_RESET (XGI_IOCTL_BASE + 6)
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#define XGI_ESC_DUMP_REGISTER (XGI_IOCTL_BASE + 7)
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#define XGI_ESC_DEBUG_INFO (XGI_IOCTL_BASE + 8)
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#define XGI_ESC_TEST_RWINKERNEL (XGI_IOCTL_BASE + 9)
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#define XGI_ESC_STATE_CHANGE (XGI_IOCTL_BASE + 10)
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#define XGI_IOCTL_DEVICE_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_DEVICE_INFO, struct xgi_chip_info)
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#define XGI_IOCTL_POST_VBIOS _IO(XGI_IOCTL_MAGIC, XGI_ESC_POST_VBIOS)
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#define XGI_IOCTL_FB_INIT _IO(XGI_IOCTL_MAGIC, XGI_ESC_FB_INIT)
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#define XGI_IOCTL_FB_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_FB_ALLOC, struct xgi_mem_alloc)
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#define XGI_IOCTL_FB_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_FB_FREE, unsigned long)
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#define XGI_IOCTL_PCIE_INIT _IO(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_INIT)
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#define XGI_IOCTL_PCIE_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_ALLOC, struct xgi_mem_alloc)
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#define XGI_IOCTL_PCIE_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_FREE, unsigned long)
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#define XGI_IOCTL_PUT_SCREEN_INFO _IOW(XGI_IOCTL_MAGIC, XGI_ESC_PUT_SCREEN_INFO, struct xgi_screen_info)
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#define XGI_IOCTL_GET_SCREEN_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_GET_SCREEN_INFO, struct xgi_screen_info)
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#define XGI_IOCTL_GE_RESET _IO(XGI_IOCTL_MAGIC, XGI_ESC_GE_RESET)
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#define XGI_IOCTL_SAREA_INFO _IOW(XGI_IOCTL_MAGIC, XGI_ESC_SAREA_INFO, struct xgi_sarea_info)
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#define XGI_IOCTL_DUMP_REGISTER _IO(XGI_IOCTL_MAGIC, XGI_ESC_DUMP_REGISTER)
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#define XGI_IOCTL_DEBUG_INFO _IO(XGI_IOCTL_MAGIC, XGI_ESC_DEBUG_INFO)
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#define XGI_IOCTL_MMIO_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_MMIO_INFO, struct xgi_mmio_info)
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#define XGI_IOCTL_SUBMIT_CMDLIST _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_SUBMIT_CMDLIST, struct xgi_cmd_info)
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#define XGI_IOCTL_TEST_RWINKERNEL _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_TEST_RWINKERNEL, unsigned long)
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#define XGI_IOCTL_STATE_CHANGE _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_STATE_CHANGE, struct xgi_state_info)
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#define XGI_IOCTL_PCIE_CHECK _IO(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_CHECK)
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#define XGI_IOCTL_MAXNR 30
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/*
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Loading…
Reference in New Issue