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[gem] Clarify use of explicit domain control. Remove Gen3 from I-cache usage.

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Keith Packard 2008-05-12 13:00:55 -07:00
parent ff39db099b
commit 6950b7da71
1 changed files with 9 additions and 3 deletions
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12
linux-core/drm-gem.txt
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@ -358,6 +358,12 @@ to be generally true, this ioctl may be simplified further.
necessary CPU flushing will occur and the object will be correctly necessary CPU flushing will occur and the object will be correctly
synchronized with the GPU. synchronized with the GPU.
Note that this synchronization is not required for any accesses
going through the driver itself. The pread, pwrite and execbuffer
ioctls all perform the necessary domain management internally.
Explicit synchronization is only necessary when accessing the object
through the mmap'd address.
7. Execution (Intel specific) 7. Execution (Intel specific)
Managing the command buffers is inherently chip-specific, so the core of gem Managing the command buffers is inherently chip-specific, so the core of gem
@ -475,9 +481,9 @@ to synchronize what is needed while leaving other cache contents intact.
needs to be flushed to the GPU. needs to be flushed to the GPU.
* DRM_GEM_DOMAIN_I915_INSTRUCTION * DRM_GEM_DOMAIN_I915_INSTRUCTION
Fragment programs on Gen3 and all of the programs on later All of the programs on Gen4 and later chips use an instruction cache to
chips use an instruction cache to speed program execution. It must be speed program execution. It must be explicitly flushed when new programs
explicitly flushed when new programs are written to memory by the CPU. are written to memory by the CPU.
* DRM_GEM_DOMAIN_I915_VERTEX * DRM_GEM_DOMAIN_I915_VERTEX
Vertex data uses two different vertex caches, but they're Vertex data uses two different vertex caches, but they're