amdgpu: add semaphore support
the semaphore is a binary semaphore. the work flow is: 1. create sem 2. signal sem 3. wait sem, reset sem after signalled 4. destroy sem. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>main
Marek Olšák
parent
f06c992819
commit
6afadeaf13
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@ -124,6 +124,11 @@ typedef struct amdgpu_bo_list *amdgpu_bo_list_handle;
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*/
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typedef struct amdgpu_va *amdgpu_va_handle;
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/**
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* Define handle for semaphore
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*/
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typedef struct amdgpu_semaphore *amdgpu_semaphore_handle;
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/*--------------------------------------------------------------------------*/
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/* -------------------------- Structures ---------------------------------- */
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/*--------------------------------------------------------------------------*/
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@ -1180,4 +1185,64 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo,
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uint64_t flags,
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uint32_t ops);
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/**
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* create semaphore
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*
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* \param sem - \c [out] semaphore handle
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*
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* \return 0 on success\n
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* <0 - Negative POSIX Error code
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*
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*/
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int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem);
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/**
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* signal semaphore
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*
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* \param context - \c [in] GPU Context
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* \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
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* \param ip_instance - \c [in] Index of the IP block of the same type
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* \param ring - \c [in] Specify ring index of the IP
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* \param sem - \c [in] semaphore handle
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*
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* \return 0 on success\n
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* <0 - Negative POSIX Error code
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*
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*/
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int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx,
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uint32_t ip_type,
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uint32_t ip_instance,
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uint32_t ring,
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amdgpu_semaphore_handle sem);
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/**
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* wait semaphore
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*
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* \param context - \c [in] GPU Context
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* \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
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* \param ip_instance - \c [in] Index of the IP block of the same type
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* \param ring - \c [in] Specify ring index of the IP
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* \param sem - \c [in] semaphore handle
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*
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* \return 0 on success\n
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* <0 - Negative POSIX Error code
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*
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*/
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int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
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uint32_t ip_type,
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uint32_t ip_instance,
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uint32_t ring,
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amdgpu_semaphore_handle sem);
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/**
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* destroy semaphore
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*
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* \param sem - \c [in] semaphore handle
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*
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* \return 0 on success\n
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* <0 - Negative POSIX Error code
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*
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*/
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int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem);
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#endif /* #ifdef _AMDGPU_H_ */
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@ -40,6 +40,9 @@
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#include "amdgpu_drm.h"
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#include "amdgpu_internal.h"
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static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle sem);
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static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem);
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/**
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* Create command submission context
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*
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@ -53,6 +56,7 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
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{
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struct amdgpu_context *gpu_context;
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union drm_amdgpu_ctx args;
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int i, j, k;
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int r;
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if (NULL == dev)
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@ -66,6 +70,10 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
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gpu_context->dev = dev;
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r = pthread_mutex_init(&gpu_context->sequence_mutex, NULL);
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if (r)
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goto error;
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/* Create the context */
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memset(&args, 0, sizeof(args));
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args.in.op = AMDGPU_CTX_OP_ALLOC_CTX;
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@ -74,11 +82,16 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
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goto error;
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gpu_context->id = args.out.alloc.ctx_id;
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for (i = 0; i < AMDGPU_HW_IP_NUM; i++)
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for (j = 0; j < AMDGPU_HW_IP_INSTANCE_MAX_COUNT; j++)
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for (k = 0; k < AMDGPU_CS_MAX_RINGS; k++)
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list_inithead(&gpu_context->sem_list[i][j][k]);
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*context = (amdgpu_context_handle)gpu_context;
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return 0;
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error:
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pthread_mutex_destroy(&gpu_context->sequence_mutex);
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free(gpu_context);
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return r;
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}
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@ -94,18 +107,32 @@ error:
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int amdgpu_cs_ctx_free(amdgpu_context_handle context)
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{
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union drm_amdgpu_ctx args;
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int i, j, k;
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int r;
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if (NULL == context)
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return -EINVAL;
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pthread_mutex_destroy(&context->sequence_mutex);
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/* now deal with kernel side */
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memset(&args, 0, sizeof(args));
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args.in.op = AMDGPU_CTX_OP_FREE_CTX;
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args.in.ctx_id = context->id;
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r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
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&args, sizeof(args));
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for (i = 0; i < AMDGPU_HW_IP_NUM; i++) {
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for (j = 0; j < AMDGPU_HW_IP_INSTANCE_MAX_COUNT; j++) {
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for (k = 0; k < AMDGPU_CS_MAX_RINGS; k++) {
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amdgpu_semaphore_handle sem;
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LIST_FOR_EACH_ENTRY(sem, &context->sem_list[i][j][k], list) {
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list_del(&sem->list);
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amdgpu_cs_reset_sem(sem);
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amdgpu_cs_unreference_sem(sem);
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}
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}
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}
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}
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free(context);
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return r;
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@ -150,7 +177,10 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context,
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struct drm_amdgpu_cs_chunk *chunks;
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struct drm_amdgpu_cs_chunk_data *chunk_data;
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struct drm_amdgpu_cs_chunk_dep *dependencies = NULL;
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uint32_t i, size;
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struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL;
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struct list_head *sem_list;
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amdgpu_semaphore_handle sem;
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uint32_t i, size, sem_count = 0;
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bool user_fence;
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int r = 0;
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@ -162,7 +192,7 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context,
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return -EINVAL;
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user_fence = (ibs_request->fence_info.handle != NULL);
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size = ibs_request->number_of_ibs + (user_fence ? 2 : 1);
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size = ibs_request->number_of_ibs + (user_fence ? 2 : 1) + 1;
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chunk_array = alloca(sizeof(uint64_t) * size);
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chunks = alloca(sizeof(struct drm_amdgpu_cs_chunk) * size);
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@ -196,6 +226,8 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context,
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chunk_data[i].ib_data.flags = ib->flags;
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}
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pthread_mutex_lock(&context->sequence_mutex);
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if (user_fence) {
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i = cs.in.num_chunks++;
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@ -240,15 +272,49 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context,
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chunks[i].chunk_data = (uint64_t)(uintptr_t)dependencies;
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}
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sem_list = &context->sem_list[ibs_request->ip_type][ibs_request->ip_instance][ibs_request->ring];
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LIST_FOR_EACH_ENTRY(sem, sem_list, list)
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sem_count++;
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if (sem_count) {
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sem_dependencies = malloc(sizeof(struct drm_amdgpu_cs_chunk_dep) * sem_count);
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if (!sem_dependencies) {
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r = -ENOMEM;
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goto error_unlock;
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}
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sem_count = 0;
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LIST_FOR_EACH_ENTRY(sem, sem_list, list) {
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struct amdgpu_cs_fence *info = &sem->signal_fence;
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struct drm_amdgpu_cs_chunk_dep *dep = &sem_dependencies[sem_count++];
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dep->ip_type = info->ip_type;
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dep->ip_instance = info->ip_instance;
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dep->ring = info->ring;
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dep->ctx_id = info->context->id;
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dep->handle = info->fence;
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list_del(&sem->list);
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amdgpu_cs_reset_sem(sem);
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amdgpu_cs_unreference_sem(sem);
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}
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i = cs.in.num_chunks++;
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/* dependencies chunk */
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chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
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chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES;
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chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4 * sem_count;
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chunks[i].chunk_data = (uint64_t)(uintptr_t)sem_dependencies;
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}
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r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CS,
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&cs, sizeof(cs));
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if (r)
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goto error_unlock;
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ibs_request->seq_no = cs.out.handle;
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context->last_seq[ibs_request->ip_type][ibs_request->ip_instance][ibs_request->ring] = ibs_request->seq_no;
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error_unlock:
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pthread_mutex_unlock(&context->sequence_mutex);
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free(dependencies);
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free(sem_dependencies);
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return r;
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}
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@ -369,3 +435,102 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
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return r;
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}
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int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem)
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{
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struct amdgpu_semaphore *gpu_semaphore;
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if (NULL == sem)
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return -EINVAL;
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gpu_semaphore = calloc(1, sizeof(struct amdgpu_semaphore));
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if (NULL == gpu_semaphore)
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return -ENOMEM;
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atomic_set(&gpu_semaphore->refcount, 1);
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*sem = gpu_semaphore;
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return 0;
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}
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int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx,
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uint32_t ip_type,
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uint32_t ip_instance,
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uint32_t ring,
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amdgpu_semaphore_handle sem)
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{
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if (NULL == ctx)
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return -EINVAL;
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if (ip_type >= AMDGPU_HW_IP_NUM)
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return -EINVAL;
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if (ring >= AMDGPU_CS_MAX_RINGS)
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return -EINVAL;
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if (NULL == sem)
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return -EINVAL;
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/* sem has been signaled */
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if (sem->signal_fence.context)
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return -EINVAL;
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pthread_mutex_lock(&ctx->sequence_mutex);
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sem->signal_fence.context = ctx;
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sem->signal_fence.ip_type = ip_type;
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sem->signal_fence.ip_instance = ip_instance;
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sem->signal_fence.ring = ring;
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sem->signal_fence.fence = ctx->last_seq[ip_type][ip_instance][ring];
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update_references(NULL, &sem->refcount);
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pthread_mutex_unlock(&ctx->sequence_mutex);
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return 0;
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}
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int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
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uint32_t ip_type,
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uint32_t ip_instance,
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uint32_t ring,
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amdgpu_semaphore_handle sem)
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{
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if (NULL == ctx)
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return -EINVAL;
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if (ip_type >= AMDGPU_HW_IP_NUM)
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return -EINVAL;
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if (ring >= AMDGPU_CS_MAX_RINGS)
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return -EINVAL;
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if (NULL == sem)
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return -EINVAL;
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/* must signal first */
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if (NULL == sem->signal_fence.context)
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return -EINVAL;
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pthread_mutex_lock(&ctx->sequence_mutex);
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list_add(&sem->list, &ctx->sem_list[ip_type][ip_instance][ring]);
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pthread_mutex_unlock(&ctx->sequence_mutex);
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return 0;
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}
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static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem)
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{
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if (NULL == sem)
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return -EINVAL;
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if (NULL == sem->signal_fence.context)
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return -EINVAL;
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sem->signal_fence.context = NULL;;
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sem->signal_fence.ip_type = 0;
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sem->signal_fence.ip_instance = 0;
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sem->signal_fence.ring = 0;
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sem->signal_fence.fence = 0;
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return 0;
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}
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static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle sem)
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{
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if (NULL == sem)
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return -EINVAL;
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if (update_references(&sem->refcount, NULL))
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free(sem);
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return 0;
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}
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int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem)
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{
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return amdgpu_cs_unreference_sem(sem);
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}
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@ -111,8 +111,23 @@ struct amdgpu_bo_list {
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struct amdgpu_context {
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struct amdgpu_device *dev;
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/** Mutex for accessing fences and to maintain command submissions
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in good sequence. */
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pthread_mutex_t sequence_mutex;
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/* context id*/
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uint32_t id;
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uint64_t last_seq[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS];
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struct list_head sem_list[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS];
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};
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/**
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* Structure describing sw semaphore based on scheduler
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*
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*/
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struct amdgpu_semaphore {
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atomic_t refcount;
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struct list_head list;
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struct amdgpu_cs_fence signal_fence;
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};
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/**
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