intel: Add Cannonlake PCI IDs for U-skus.
Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is a copy of merged i915's commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.") v2: Remove PCI IDs for SKU not mentioned in spec. v3: Add kernel commit id for reference. Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>main
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@ -233,6 +233,11 @@
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#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7
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#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8
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#define PCI_CHIP_CANNONLAKE_U_GT2_0 0x5A52
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#define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A
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#define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42
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#define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A
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#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
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(devid) == PCI_CHIP_I915_GM || \
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(devid) == PCI_CHIP_I945_GM || \
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@ -496,5 +501,13 @@
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IS_GEN8(dev) || \
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IS_GEN9(dev))
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#define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \
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(devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \
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(devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \
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(devid) == PCI_CHIP_CANNONLAKE_U_GT2_3)
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#define IS_CANNONLAKE(devid) (IS_CNL_U(devid))
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#define IS_GEN10(devid) (IS_CANNONLAKE(devid))
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#endif /* _INTEL_CHIPSET_H */
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