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nouveau: simplify and fix BIG_ENDIAN flags

main
Patrice Mandin 2007-01-25 23:06:48 +01:00
parent 582637641a
commit 6d9ef1a960
1 changed files with 21 additions and 27 deletions
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46
shared-core/nouveau_fifo.c
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@ -182,16 +182,15 @@ int nouveau_fifo_init(drm_device_t *dev)
NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000); NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000);
NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000); NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000);
NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000); NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000);
#ifdef __BIG_ENDIAN
NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES | NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES | NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
NV_PFIFO_CACH1_DMAF_MAX_REQS_4 | NV_PFIFO_CACH1_DMAF_MAX_REQS_4 |
NV_PFIFO_CACH1_BIG_ENDIAN); #ifdef __BIG_ENDIAN
#else NV_PFIFO_CACH1_BIG_ENDIAN |
NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
#endif #endif
0x00000000);
NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001); NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001);
NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001); NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001);
NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001);
@ -283,16 +282,14 @@ static void nouveau_nv04_context_init(drm_device_t *dev,
RAMFC_WR(DMA_PUT , init->put_base); RAMFC_WR(DMA_PUT , init->put_base);
RAMFC_WR(DMA_GET , init->put_base); RAMFC_WR(DMA_GET , init->put_base);
RAMFC_WR(DMA_INSTANCE , nouveau_chip_instance_get(dev, cb_obj->instance)); RAMFC_WR(DMA_INSTANCE , nouveau_chip_instance_get(dev, cb_obj->instance));
#ifdef __BIG_ENDIAN
RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES | RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES | NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
NV_PFIFO_CACH1_DMAF_MAX_REQS_4 | NV_PFIFO_CACH1_DMAF_MAX_REQS_4 |
NV_PFIFO_CACH1_BIG_ENDIAN); #ifdef __BIG_ENDIAN
#else NV_PFIFO_CACH1_BIG_ENDIAN |
RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
#endif #endif
0x00000000);
} }
#undef RAMFC_WR #undef RAMFC_WR
@ -318,17 +315,14 @@ static void nouveau_nv10_context_init(drm_device_t *dev,
RAMFC_WR(DMA_GET , init->put_base); RAMFC_WR(DMA_GET , init->put_base);
RAMFC_WR(DMA_INSTANCE , nouveau_chip_instance_get(dev, RAMFC_WR(DMA_INSTANCE , nouveau_chip_instance_get(dev,
cb_obj->instance)); cb_obj->instance));
#ifdef __BIG_ENDIAN
RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
NV_PFIFO_CACH1_DMAF_MAX_REQS_4 |
NV_PFIFO_CACH1_BIG_ENDIAN);
#else
RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES | RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES | NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
NV_PFIFO_CACH1_DMAF_MAX_REQS_4); NV_PFIFO_CACH1_DMAF_MAX_REQS_4 |
#ifdef __BIG_ENDIAN
NV_PFIFO_CACH1_BIG_ENDIAN |
#endif #endif
0x00000000);
} }
static void nouveau_nv30_context_init(drm_device_t *dev, static void nouveau_nv30_context_init(drm_device_t *dev,
@ -358,9 +352,8 @@ static void nouveau_nv30_context_init(drm_device_t *dev,
NV_PFIFO_CACH1_DMAF_MAX_REQS_8 | NV_PFIFO_CACH1_DMAF_MAX_REQS_8 |
#ifdef __BIG_ENDIAN #ifdef __BIG_ENDIAN
NV_PFIFO_CACH1_BIG_ENDIAN | NV_PFIFO_CACH1_BIG_ENDIAN |
#else
0x00000000);
#endif #endif
0x00000000);
RAMFC_WR(ENGINE, NV_READ(NV_PFIFO_CACH1_ENG)); RAMFC_WR(ENGINE, NV_READ(NV_PFIFO_CACH1_ENG));
RAMFC_WR(PULL1_ENGINE, NV_READ(NV_PFIFO_CACH1_PUL1)); RAMFC_WR(PULL1_ENGINE, NV_READ(NV_PFIFO_CACH1_PUL1));
@ -489,11 +482,14 @@ nouveau_fifo_context_restore(drm_device_t *dev, int channel)
NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000); NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000);
NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000); NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000);
NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000); NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000);
NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
NV_PFIFO_CACH1_DMAF_MAX_REQS_4 |
#ifdef __BIG_ENDIAN #ifdef __BIG_ENDIAN
NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN); NV_PFIFO_CACH1_BIG_ENDIAN |
#else
NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
#endif #endif
0x00000000);
} }
/* allocates and initializes a fifo for user space consumption */ /* allocates and initializes a fifo for user space consumption */
@ -741,5 +737,3 @@ drm_ioctl_desc_t nouveau_ioctls[] = {
}; };
int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls); int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);