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intel: Add a function for setting (GTT,GTT) domain, for use by UXA. 

This function can also serve the role that the bo_wait_rendering did, when
write_enable is unset.
main
Eric Anholt 2008-11-13 11:44:22 -08:00
parent 7e4e0fbbb8
commit 6fb1ad767d
2 changed files with 16 additions and 1 deletions
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1
libdrm/intel/intel_bufmgr.h
View File

@ -106,6 +106,7 @@ drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
unsigned int handle);
void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr);
int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
/* drm_intel_bufmgr_fake.c */
drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd,

16
libdrm/intel/intel_bufmgr_gem.c
View File

@ -729,8 +729,22 @@ drm_intel_gem_bo_get_subdata (drm_intel_bo *bo, unsigned long offset,
return 0;
}
/** Waits for all GPU rendering to the object to have completed. */
static void
drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
{
return drm_intel_gem_bo_start_gtt_access(bo, 0);
}
/**
* Sets the object to the GTT read and possibly write domain, used by the X
* 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
*
* In combination with drm_intel_gem_bo_pin() and manual fence management, we
* can do tiled pixmaps this way.
*/
void
drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
@ -739,7 +753,7 @@ drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
set_domain.handle = bo_gem->gem_handle;
set_domain.read_domains = I915_GEM_DOMAIN_GTT;
set_domain.write_domain = 0;
set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
do {
ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
} while (ret == -1 && errno == EINTR);