Restructure initialisation a bit.
- Do important card init in firstopen
- Give each channel it's own cmdbuf dma object
- Move RAMHT config state to the same place as RAMRO/RAMFC
- Make sure instance mem for objects is *after* RAM{FC,HT,RO}
main
Ben Skeggs
parent
35bf8fb5cf
commit
7002082944
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@ -71,16 +71,14 @@ struct nouveau_fifo
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drm_local_map_t *map;
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/* mapping of the regs controling the fifo */
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drm_local_map_t *regs;
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/* dma object for the command buffer itself */
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struct nouveau_object *cmdbuf_obj;
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/* objects belonging to this fifo */
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struct nouveau_object *objs;
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};
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struct nouveau_object_store
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{
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int ht_bits;
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int ht_size;
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int ht_base;
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uint32_t *inst_bmap;
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uint32_t first_instance;
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int num_instance;
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@ -116,7 +114,6 @@ typedef struct drm_nouveau_private {
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int cur_fifo;
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struct nouveau_object *fb_obj;
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struct nouveau_object *cmdbuf_obj;
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int cmdbuf_ch_size;
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struct mem_block* cmdbuf_alloc;
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@ -124,8 +121,13 @@ typedef struct drm_nouveau_private {
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struct nouveau_fifo fifos[NV_MAX_FIFO_NUMBER];
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struct nouveau_object_store objs;
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/* RAMFC and RAMRO offsets */
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uint32_t ramht_offset;
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uint32_t ramht_size;
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uint32_t ramht_bits;
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uint32_t ramfc_offset;
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uint32_t ramfc_size;
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uint32_t ramro_offset;
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uint32_t ramro_size;
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struct mem_block *agp_heap;
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struct mem_block *fb_heap;
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@ -155,12 +157,13 @@ extern int nouveau_mem_init(struct drm_device *dev);
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extern void nouveau_mem_close(struct drm_device *dev);
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/* nouveau_fifo.c */
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extern int nouveau_fifo_init(drm_device_t *dev);
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extern int nouveau_fifo_number(drm_device_t *dev);
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extern void nouveau_fifo_cleanup(drm_device_t *dev, DRMFILE filp);
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extern int nouveau_fifo_id_get(drm_device_t *dev, DRMFILE filp);
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/* nouveau_object.c */
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extern void nouveau_hash_table_init(drm_device_t *dev);
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extern int nouveau_object_init(drm_device_t *dev);
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extern void nouveau_object_cleanup(drm_device_t *dev, DRMFILE filp);
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extern struct nouveau_object *nouveau_dma_object_create(drm_device_t *dev,
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uint32_t offset, uint32_t size, int access, uint32_t target);
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@ -53,63 +53,111 @@ int nouveau_fifo_number(drm_device_t* dev)
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* voir nv_driver.c : NVPreInit
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*/
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static void nouveau_fifo_init(drm_device_t* dev)
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static int nouveau_fifo_instmem_configure(drm_device_t *dev)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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/* Init PFIFO - This is an exact copy of what's done in the Xorg ddx so far.
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* We should be able to figure out what's happening from the
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* resources available..
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int i;
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/* Clear RAMIN */
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for (i=0x00710000; i<0x00800000; i++)
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NV_WRITE(i, 0x00000000);
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/* FIFO hash table (RAMHT)
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* use 4k hash table at RAMIN+0x10000
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* TODO: extend the hash table
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*/
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dev_priv->ramht_offset = 0x10000;
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dev_priv->ramht_bits = 9;
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dev_priv->ramht_size = (1 << dev_priv->ramht_bits);
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NV_WRITE(NV_PFIFO_RAMHT,
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(0x03 << 24) /* search 128 */ |
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((dev_priv->ramht_bits - 9) << 16) |
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(dev_priv->ramht_offset >> 8)
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);
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DRM_DEBUG("RAMHT offset=0x%x, size=%d\n",
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dev_priv->ramht_offset,
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dev_priv->ramht_size);
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if (dev->irq_enabled)
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nouveau_irq_postinstall(dev);
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/* FIFO runout table (RAMRO) - 512k at 0x11200 */
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dev_priv->ramro_offset = 0x11200;
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dev_priv->ramro_size = 512;
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NV_WRITE(NV_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
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DRM_DEBUG("RAMRO offset=0x%x, size=%d\n",
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dev_priv->ramro_offset,
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dev_priv->ramro_size);
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if (dev_priv->card_type >= NV_40)
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NV_WRITE(NV_PGRAPH_NV40_UNK220, dev_priv->fb_obj->instance >> 4);
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/* FIFO context table (RAMFC)
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* NV40 : Not sure exactly how to position RAMFC on some cards,
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* 0x30002 seems to position it at RAMIN+0x20000 on these
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* cards. RAMFC is 4kb (32 fifos, 128byte entries).
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* Others: Position RAMFC at RAMIN+0x11400
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*/
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if (dev_priv->card_type >= NV_40) {
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dev_priv->ramfc_offset = 0x20000;
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dev_priv->ramfc_size = nouveau_fifo_number(dev) * 128;
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NV_WRITE(NV40_PFIFO_RAMFC, 0x30002);
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} else if (dev_priv->card_type >= NV_10) {
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dev_priv->ramfc_offset = 0x11400;
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dev_priv->ramfc_size = nouveau_fifo_number(dev) * 64;
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NV_WRITE(NV_PFIFO_RAMFC, dev_priv->ramfc_offset>>8);
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} else {
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dev_priv->ramfc_offset = 0x11400;
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dev_priv->ramfc_size = nouveau_fifo_number(dev) * 32;
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NV_WRITE(NV_PFIFO_RAMFC, dev_priv->ramfc_offset>>8);
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}
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DRM_DEBUG("RAMFC offset=0x%x, size=%d\n",
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dev_priv->ramfc_offset,
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dev_priv->ramfc_size);
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DRM_DEBUG("%s: setting FIFO %d active\n", __func__, dev_priv->cur_fifo);
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return 0;
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}
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int nouveau_fifo_init(drm_device_t *dev)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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int ret;
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// FIXME remove all the stuff that's done in nouveau_fifo_alloc
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NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
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ret = nouveau_fifo_instmem_configure(dev);
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if (ret) {
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DRM_ERROR("Failed to configure instance memory\n");
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return ret;
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}
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/* FIXME remove all the stuff that's done in nouveau_fifo_alloc */
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DRM_DEBUG("Setting defaults for remaining PFIFO regs\n");
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/* All channels into PIO mode */
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NV_WRITE(NV_PFIFO_MODE, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000);
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if (dev_priv->card_type >= NV_40)
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NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00010000|dev_priv->cur_fifo);
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else
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NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000100|dev_priv->cur_fifo);
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NV_WRITE(NV_PFIFO_CACH1_DMAP, dev_priv->cur_fifo * dev_priv->cmdbuf_ch_size);
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NV_WRITE(NV_PFIFO_CACH1_DMAG, dev_priv->cur_fifo * dev_priv->cmdbuf_ch_size);
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NV_WRITE(NV_PFIFO_CACH1_DMAI, dev_priv->cmdbuf_obj->instance >> 4);
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/* Channel 0 active, PIO mode */
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NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000000);
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/* PUT and GET to 0 */
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NV_WRITE(NV_PFIFO_CACH1_DMAP, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH1_DMAP, 0x00000000);
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/* No cmdbuf object */
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NV_WRITE(NV_PFIFO_CACH1_DMAI, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH0_PSH0, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH0_PUL0, 0x00000000);
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NV_WRITE(NV_PFIFO_SIZE , 0x0000FFFF);
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NV_WRITE(NV_PFIFO_SIZE, 0x0000FFFF);
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NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF);
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NV_WRITE(NV_PFIFO_RAMHT,
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(0x03 << 24) /* search 128 */ |
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((dev_priv->objs.ht_bits - 9) << 16) |
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(dev_priv->objs.ht_base >> 8)
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);
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/* RAMFC needs to be at RAMIN+0x20000 on NV40, I currently don't know
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* how to move it..
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*/
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dev_priv->ramfc_offset=0x20000;
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if (dev_priv->card_type < NV_40)
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NV_WRITE(NV_PFIFO_RAMFC, dev_priv->ramfc_offset>>8); /* RAMIN+0x11000 0.5k */
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else
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NV_WRITE(0x2220, 0x30002);
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dev_priv->ramro_offset=0x11200;
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NV_WRITE(NV_PFIFO_RAMRO, dev_priv->ramro_offset>>8); /* RAMIN+0x11200 0.5k */
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NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001);
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NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000);
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#ifdef __BIG_ENDIAN
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NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN);
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NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
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NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
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NV_PFIFO_CACH1_DMAF_MAX_REQS_4 |
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NV_PFIFO_CACH1_BIG_ENDIAN);
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#else
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NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
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NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
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NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
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NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
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#endif
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NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001);
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NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001);
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@ -126,11 +174,7 @@ static void nouveau_fifo_init(drm_device_t* dev)
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NV_WRITE(NV_PFIFO_DMA_TIMESLICE, 0x001fffff);
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NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
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DRM_DEBUG("%s: CACHE1 GET/PUT readback %d/%d\n", __func__,
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NV_READ(NV_PFIFO_CACH1_DMAG),
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NV_READ(NV_PFIFO_CACH1_DMAP));
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DRM_INFO("%s: OK\n", __func__);
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return 0;
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}
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static int nouveau_dma_init(struct drm_device *dev)
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@ -140,14 +184,6 @@ static int nouveau_dma_init(struct drm_device *dev)
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struct mem_block *cb;
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int cb_min_size = nouveau_fifo_number(dev) * max(NV03_FIFO_SIZE,PAGE_SIZE);
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/* XXX this should be done earlier on init */
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nouveau_hash_table_init(dev);
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if (dev_priv->card_type >= NV_40)
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dev_priv->fb_obj = nouveau_dma_object_create(dev,
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0, nouveau_mem_fb_amount(dev),
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NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM);
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/* Defaults for unconfigured values */
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if (!config->cmdbuf.location)
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config->cmdbuf.location = NOUVEAU_MEM_FB;
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@ -168,13 +204,6 @@ static int nouveau_dma_init(struct drm_device *dev)
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return DRM_ERR(ENOMEM);
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}
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if (config->cmdbuf.location == NOUVEAU_MEM_AGP)
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dev_priv->cmdbuf_obj = nouveau_dma_object_create(dev,
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cb->start, cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_AGP);
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else
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dev_priv->cmdbuf_obj = nouveau_dma_object_create(dev,
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cb->start - drm_get_resource_start(dev, 1),
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cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM);
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dev_priv->cmdbuf_ch_size = (uint32_t)cb->size / nouveau_fifo_number(dev);
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dev_priv->cmdbuf_alloc = cb;
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@ -190,6 +219,7 @@ static void nouveau_context_init(drm_device_t *dev,
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drm_nouveau_fifo_alloc_t *init)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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struct nouveau_object *cb_obj;
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uint32_t ctx_addr,ctx_size;
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int i;
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@ -208,6 +238,8 @@ static void nouveau_context_init(drm_device_t *dev,
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break;
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}
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cb_obj = dev_priv->fifos[init->channel].cmdbuf_obj;
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ctx_addr=NV_RAMIN+dev_priv->ramfc_offset+init->channel*ctx_size;
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// clear the fifo context
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for(i=0;i<ctx_size/4;i++)
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@ -218,7 +250,7 @@ static void nouveau_context_init(drm_device_t *dev,
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if (dev_priv->card_type <= NV_05)
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{
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// that's what is done in nvosdk, but that part of the code is buggy so...
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NV_WRITE(ctx_addr+8,dev_priv->cmdbuf_obj->instance >> 4);
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NV_WRITE(ctx_addr+8, cb_obj->instance >> 4);
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#ifdef __BIG_ENDIAN
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NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN);
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#else
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@ -227,7 +259,7 @@ static void nouveau_context_init(drm_device_t *dev,
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}
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else
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{
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NV_WRITE(ctx_addr+12,dev_priv->cmdbuf_obj->instance >> 4/*DMA INST/DMA COUNT*/);
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NV_WRITE(ctx_addr+12,cb_obj->instance >> 4/*DMA INST/DMA COUNT*/);
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#ifdef __BIG_ENDIAN
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NV_WRITE(ctx_addr+20,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN);
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#else
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@ -242,9 +274,11 @@ static void nouveau_nv40_context_init(drm_device_t *dev,
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drm_nouveau_fifo_alloc_t *init)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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struct nouveau_object *cb_obj;
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uint32_t fifoctx;
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int i;
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cb_obj = dev_priv->fifos[init->channel].cmdbuf_obj;
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fifoctx = NV_RAMIN + dev_priv->ramfc_offset + init->channel*128;
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for (i=0;i<128;i+=4)
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NV_WRITE(fifoctx + i, 0);
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@ -254,7 +288,7 @@ static void nouveau_nv40_context_init(drm_device_t *dev,
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*/
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RAMFC_WR(DMA_PUT , init->put_base);
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RAMFC_WR(DMA_GET , init->put_base);
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RAMFC_WR(DMA_INSTANCE , dev_priv->cmdbuf_obj->instance >> 4);
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RAMFC_WR(DMA_INSTANCE , cb_obj->instance >> 4);
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RAMFC_WR(DMA_FETCH , 0x30086078);
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RAMFC_WR(DMA_SUBROUTINE, init->put_base);
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RAMFC_WR(GRCTX_INSTANCE, 0); /* XXX */
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@ -296,6 +330,7 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init,
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int i;
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int ret;
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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struct nouveau_object *cb_obj;
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/* Init cmdbuf on first FIFO init, this is delayed until now to
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* give the ddx a chance to configure the cmdbuf with SETPARAM
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@ -305,9 +340,6 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init,
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if (ret)
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return ret;
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}
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/* Initialise PFIFO regs */
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if (!dev_priv->fifo_alloc_count)
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nouveau_fifo_init(dev);
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/*
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* Alright, here is the full story
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@ -326,6 +358,23 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init,
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if (i==nouveau_fifo_number(dev))
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return DRM_ERR(EINVAL);
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/* allocate a dma object for the command buffer */
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if (dev_priv->cmdbuf_alloc->flags & NOUVEAU_MEM_AGP) {
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cb_obj = nouveau_dma_object_create(dev,
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dev_priv->cmdbuf_alloc->start,
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dev_priv->cmdbuf_alloc->size,
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NV_DMA_ACCESS_RO,
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NV_DMA_TARGET_AGP);
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} else {
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cb_obj = nouveau_dma_object_create(dev,
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dev_priv->cmdbuf_alloc->start -
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drm_get_resource_start(dev, 1),
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dev_priv->cmdbuf_alloc->size,
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NV_DMA_ACCESS_RO,
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NV_DMA_TARGET_VIDMEM);
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}
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dev_priv->fifos[i].cmdbuf_obj = cb_obj;
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/* that fifo is used */
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dev_priv->fifos[i].used=1;
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dev_priv->fifos[i].filp=filp;
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@ -370,7 +419,7 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init,
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NV_WRITE(NV_PFIFO_CACH1_DMAP, init->put_base);
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NV_WRITE(NV_PFIFO_CACH1_DMAG, init->put_base);
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NV_WRITE(NV_PFIFO_CACH1_DMAI, dev_priv->cmdbuf_obj->instance >> 4);
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NV_WRITE(NV_PFIFO_CACH1_DMAI, cb_obj->instance >> 4);
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NV_WRITE(NV_PFIFO_SIZE , 0x0000FFFF);
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NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF);
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|
|
@ -132,15 +132,14 @@ static uint32_t nouveau_handle_hash(drm_device_t* dev, uint32_t handle,
|
|||
int fifo)
|
||||
{
|
||||
drm_nouveau_private_t *dev_priv=dev->dev_private;
|
||||
struct nouveau_object_store *objs=&dev_priv->objs;
|
||||
uint32_t hash = 0;
|
||||
int i;
|
||||
|
||||
for (i=32;i>0;i-=objs->ht_bits) {
|
||||
hash ^= (handle & ((1 << objs->ht_bits) - 1));
|
||||
handle >>= objs->ht_bits;
|
||||
for (i=32;i>0;i-=dev_priv->ramht_bits) {
|
||||
hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1));
|
||||
handle >>= dev_priv->ramht_bits;
|
||||
}
|
||||
hash ^= fifo << (objs->ht_bits - 4);
|
||||
hash ^= fifo << (dev_priv->ramht_bits - 4);
|
||||
return hash << 3;
|
||||
}
|
||||
|
||||
|
|
@ -148,9 +147,8 @@ static int nouveau_hash_table_insert(drm_device_t* dev, int fifo,
|
|||
struct nouveau_object *obj)
|
||||
{
|
||||
drm_nouveau_private_t *dev_priv=dev->dev_private;
|
||||
struct nouveau_object_store *objs=&dev_priv->objs;
|
||||
int ht_base = NV_RAMIN + objs->ht_base;
|
||||
int ht_end = ht_base + objs->ht_size;
|
||||
int ht_base = NV_RAMIN + dev_priv->ramht_offset;
|
||||
int ht_end = ht_base + dev_priv->ramht_size;
|
||||
int o_ofs, ofs;
|
||||
|
||||
o_ofs = ofs = nouveau_handle_hash(dev, obj->handle, fifo);
|
||||
|
|
@ -277,38 +275,18 @@ static void nouveau_object_instance_free(drm_device_t *dev,
|
|||
objs->free_instance++;
|
||||
}
|
||||
|
||||
/* Where is the hash table located:
|
||||
|
||||
Base address and size can be calculated from this register:
|
||||
|
||||
ht_base = 0x1000 * GetBitField (pNv->PFIFO[0x0210/4],8:4);
|
||||
ht_size = 0x1000 << GetBitField (pNv->PFIFO[0x0210/4],17:16);
|
||||
|
||||
and the hash table will be located between address PRAMIN + ht_base and
|
||||
PRAMIN + ht_base + ht_size. Each hash table entry has two longwords.
|
||||
*/
|
||||
void nouveau_hash_table_init(drm_device_t* dev)
|
||||
int nouveau_object_init(drm_device_t* dev)
|
||||
{
|
||||
drm_nouveau_private_t *dev_priv=dev->dev_private;
|
||||
int i;
|
||||
|
||||
dev_priv->objs.ht_bits = 9;
|
||||
dev_priv->objs.ht_base = 0x10000;
|
||||
dev_priv->objs.ht_size = (1 << dev_priv->objs.ht_bits);
|
||||
|
||||
dev_priv->objs.first_instance = 0x13000;
|
||||
dev_priv->objs.first_instance =
|
||||
dev_priv->ramfc_offset +dev_priv->ramfc_size;
|
||||
dev_priv->objs.free_instance = 1024; /*FIXME*/
|
||||
dev_priv->objs.num_instance = 1024; /*FIXME*/
|
||||
dev_priv->objs.inst_bmap = drm_calloc
|
||||
(1, dev_priv->objs.num_instance/32, DRM_MEM_DRIVER);
|
||||
|
||||
/* clear all of RAMIN
|
||||
* NOTE: except the bottom 0x10000 bytes, the binary driver doesn't
|
||||
* like this and will die either sometime during init, or during
|
||||
* shutdown - leaving the screen in an unusable state...
|
||||
*/
|
||||
for (i=0x00710000; i<0x00800000; i+=4)
|
||||
NV_WRITE(i, 0x00000000);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -85,6 +85,7 @@
|
|||
#define NV_PFIFO_RAMHT 0x00002210
|
||||
#define NV_PFIFO_RAMFC 0x00002214
|
||||
#define NV_PFIFO_RAMRO 0x00002218
|
||||
#define NV40_PFIFO_RAMFC 0x00002220
|
||||
#define NV_PFIFO_CACHES 0x00002500
|
||||
#define NV_PFIFO_MODE 0x00002504
|
||||
#define NV_PFIFO_DMA 0x00002508
|
||||
|
|
|
|||
|
|
@ -64,6 +64,25 @@ int nouveau_firstopen(struct drm_device *dev)
|
|||
|
||||
DRM_INFO("%lld MB of video ram detected\n",nouveau_mem_fb_amount(dev)>>20);
|
||||
|
||||
/* Clear RAMIN
|
||||
* Determine locations for RAMHT/FC/RO
|
||||
* Initialise PFIFO
|
||||
*/
|
||||
ret = nouveau_fifo_init(dev);
|
||||
if (ret) return ret;
|
||||
/* Initialise instance memory allocation */
|
||||
ret = nouveau_object_init(dev);
|
||||
if (ret) return ret;
|
||||
|
||||
/* FIXME: doesn't belong here, and have no idea what it's for.. */
|
||||
if (dev_priv->card_type >= NV_40) {
|
||||
dev_priv->fb_obj = nouveau_dma_object_create(dev,
|
||||
0, nouveau_mem_fb_amount(dev),
|
||||
NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM);
|
||||
|
||||
NV_WRITE(NV_PGRAPH_NV40_UNK220, dev_priv->fb_obj->instance >> 4);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue