NV50: Implement DPMS.
parent
d88616555d
commit
701011224c
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@ -96,6 +96,43 @@ static int nv50_dac_set_clock_mode(struct nv50_output *output)
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return 0;
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}
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static int nv50_dac_set_power_mode(struct nv50_output *output, int mode)
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{
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struct drm_nouveau_private *dev_priv = output->dev->dev_private;
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uint32_t val;
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int or = nv50_output_or_offset(output);
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NV50_DEBUG("or %d\n", or);
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/* wait for it to be done */
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while (NV_READ(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or)) & NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING);
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val = NV_READ(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or)) & ~0x7F;
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if (mode != DPMSModeOn)
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val |= NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_BLANKED;
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switch (mode) {
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case DPMSModeStandby:
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val |= NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_HSYNC_OFF;
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break;
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case DPMSModeSuspend:
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val |= NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_VSYNC_OFF;
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break;
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case DPMSModeOff:
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val |= NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_OFF;
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val |= NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_HSYNC_OFF;
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val |= NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_VSYNC_OFF;
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break;
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default:
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break;
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}
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NV_WRITE(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or), val | NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING);
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return 0;
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}
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static int nv50_dac_destroy(struct nv50_output *output)
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{
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struct drm_device *dev = output->dev;
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@ -172,6 +209,7 @@ int nv50_dac_create(struct drm_device *dev, int dcb_entry)
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output->validate_mode = nv50_dac_validate_mode;
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output->execute_mode = nv50_dac_execute_mode;
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output->set_clock_mode = nv50_dac_set_clock_mode;
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output->set_power_mode = nv50_dac_set_power_mode;
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output->detect = NULL; /* TODO */
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output->destroy = nv50_dac_destroy;
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@ -640,6 +640,18 @@ int nv50_kms_crtc_set_config(struct drm_mode_set *set)
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/* next line changes crtc, so putting it here is important */
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display->last_crtc = crtc->index;
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/* this is executed immediately */
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list_for_each_entry(output, &display->outputs, head) {
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if (output->crtc != crtc)
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continue;
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rval = output->set_power_mode(output, DPMSModeOn);
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if (rval != 0) {
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DRM_ERROR("output set power mode failed\n");
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goto out;
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}
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}
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/* blank any unused crtcs */
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list_for_each_entry(crtc, &display->crtcs, head) {
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if (!(crtc_mask & (1 << crtc->index)))
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@ -654,9 +666,6 @@ int nv50_kms_crtc_set_config(struct drm_mode_set *set)
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return 0;
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out:
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if (display)
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display->update(display);
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kfree(hw_mode);
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if (rval != 0)
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@ -938,12 +947,31 @@ static void nv50_kms_connector_fill_modes(struct drm_connector *drm_connector, u
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}
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}
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static bool nv50_kms_connector_set_property(struct drm_connector *connector,
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struct drm_property *property,
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uint64_t value)
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{
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struct drm_device *dev = connector->dev;
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if (property == dev->mode_config.dpms_property && connector->encoder) {
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struct nv50_output *output = to_nv50_output(connector->encoder);
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if (!output->set_power_mode(output, (int) value))
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return true;
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else
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return false;
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}
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return false;
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}
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static const struct drm_connector_funcs nv50_kms_connector_funcs = {
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.save = NULL,
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.restore = NULL,
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.detect = nv50_kms_connector_detect,
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.destroy = nv50_kms_connector_destroy,
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.fill_modes = nv50_kms_connector_fill_modes,
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.set_property = nv50_kms_connector_set_property
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};
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static int nv50_kms_connectors_init(struct drm_device *dev)
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@ -49,6 +49,8 @@ struct nv50_output {
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int (*validate_mode) (struct nv50_output *output, struct nouveau_hw_mode *mode);
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int (*execute_mode) (struct nv50_output *output, bool disconnect);
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int (*set_clock_mode) (struct nv50_output *output);
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/* this is not a normal modeset call, it is a direct register write, so it's executed immediately */
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int (*set_power_mode) (struct nv50_output *output, int mode);
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bool (*detect) (struct nv50_output *output);
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int (*destroy) (struct nv50_output *output);
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};
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@ -114,6 +114,29 @@ static int nv50_sor_set_clock_mode(struct nv50_output *output)
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return 0;
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}
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static int nv50_sor_set_power_mode(struct nv50_output *output, int mode)
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{
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struct drm_nouveau_private *dev_priv = output->dev->dev_private;
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uint32_t val;
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int or = nv50_output_or_offset(output);
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NV50_DEBUG("or %d\n", nv50_output_or_offset(output));
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/* wait for it to be done */
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while (NV_READ(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or)) & NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING);
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val = NV_READ(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or));
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if (mode == DPMSModeOn)
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val |= NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_ON;
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else
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val &= ~NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_ON;
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NV_WRITE(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or), val | NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING);
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return 0;
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}
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static int nv50_sor_destroy(struct nv50_output *output)
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{
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struct drm_device *dev = output->dev;
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@ -194,6 +217,7 @@ int nv50_sor_create(struct drm_device *dev, int dcb_entry)
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output->validate_mode = nv50_sor_validate_mode;
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output->execute_mode = nv50_sor_execute_mode;
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output->set_clock_mode = nv50_sor_set_clock_mode;
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output->set_power_mode = nv50_sor_set_power_mode;
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output->detect = NULL;
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output->destroy = nv50_sor_destroy;
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