intel: Limit tiled pitches to 8192 on pre-i965.
Fixes: Bug 28515 - Failed to allocate framebuffer when exceed 2048 width https://bugs.freedesktop.org/show_bug.cgi?id=28515 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>main
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6ea2bda5f5
commit
726210f87d
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@ -254,7 +254,7 @@ drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
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*/
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static unsigned long
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drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
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unsigned long pitch, uint32_t tiling_mode)
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unsigned long pitch, uint32_t *tiling_mode)
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{
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unsigned long tile_width;
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unsigned long i;
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@ -262,10 +262,10 @@ drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
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/* If untiled, then just align it so that we can do rendering
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* to it with the 3D engine.
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*/
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if (tiling_mode == I915_TILING_NONE)
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if (*tiling_mode == I915_TILING_NONE)
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return ALIGN(pitch, 64);
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if (tiling_mode == I915_TILING_X)
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if (*tiling_mode == I915_TILING_X)
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tile_width = 512;
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else
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tile_width = 128;
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@ -274,6 +274,14 @@ drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
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if (bufmgr_gem->gen >= 4)
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return ROUND_UP_TO(pitch, tile_width);
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/* The older hardware has a maximum pitch of 8192 with tiled
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* surfaces, so fallback to untiled if it's too large.
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*/
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if (pitch > 8192) {
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*tiling_mode = I915_TILING_NONE;
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return ALIGN(pitch, 64);
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}
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/* Pre-965 needs power of two tile width */
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for (i = tile_width; i < pitch; i <<= 1)
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;
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@ -738,7 +746,7 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
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aligned_y = ALIGN(y, 32);
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stride = x * cpp;
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stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling);
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stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
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size = stride * aligned_y;
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size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
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} while (*tiling_mode != tiling);
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