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nv04-nv40: correct RAMHT size

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Ben Skeggs 2008-11-13 13:04:21 +11:00
parent 27fae00685
commit 753d4c39ff
2 changed files with 3 additions and 7 deletions
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7
shared-core/nouveau_object.c
View File

@ -141,13 +141,8 @@ nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
ref->channel, co, INSTANCE_RD(ramht, co/4));
co += 8;
if (co >= dev_priv->ramht_size) {
DRM_INFO("no space left after collision\n");
if (co >= dev_priv->ramht_size)
co = 0;
/* exit as it seems to cause crash with nouveau_demo and
* 0xdead0001 object */
break;
}
} while (co != ho);
DRM_ERROR("RAMHT space exhausted. ch=%d\n", ref->channel);

3
shared-core/nv04_instmem.c
View File

@ -41,7 +41,8 @@ nv04_instmem_configure_fixed_tables(struct drm_device *dev)
*/
dev_priv->ramht_offset = 0x10000;
dev_priv->ramht_bits = 9;
dev_priv->ramht_size = (1 << dev_priv->ramht_bits);
dev_priv->ramht_size = (1 << dev_priv->ramht_bits); /* nr entries */
dev_priv->ramht_size *= 8; /* 2 32-bit values per entry in RAMHT */
DRM_DEBUG("RAMHT offset=0x%x, size=%d\n", dev_priv->ramht_offset,
dev_priv->ramht_size);