Make sure PLLs are enabled before writing pipe configuration regs
Fix from the X driver. Make sure the PLLs are enabled and not in VGA mode before writing PIPE(A|B)CONF regs to avoid hangs or crashes.main
parent
c2f80ecf4b
commit
793cd1dad5
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@ -431,7 +431,11 @@ static int i915_resume(struct drm_device *dev)
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I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
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I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
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}
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I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
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if ((dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) &&
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(dev_priv->saveDPLL_A & DPLL_VGA_MODE_DIS))
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I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
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i915_restore_palette(dev, PIPE_A);
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/* Enable the plane */
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I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
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@ -471,7 +475,10 @@ static int i915_resume(struct drm_device *dev)
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I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
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I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
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}
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I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
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if ((dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) &&
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(dev_priv->saveDPLL_B & DPLL_VGA_MODE_DIS))
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I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
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i915_restore_palette(dev, PIPE_A);
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/* Enable the plane */
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I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
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