radeon: add more packet3 relocations handling
Jerome Glisse
parent
751d024dd5
commit
7abb8416a7
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@ -180,7 +180,6 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
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struct drm_radeon_cs *cs = data;
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uint32_t *packets = NULL;
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uint32_t cs_id;
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uint32_t card_offset;
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long size;
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int r;
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struct drm_radeon_kernel_chunk chunk_fake[1];
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@ -280,12 +279,11 @@ static __inline__ int radeon_cs_relocate_packet0(struct drm_radeon_cs_parser *pa
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old kernels ignore it. */
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if (parser->reloc_index == -1) {
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if (packet3_hdr != (RADEON_CP_PACKET3 | RADEON_CP_NOP | (RELOC_SIZE << 16))) {
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DRM_ERROR("Packet 3 was %x should have been %x: reg is %x\n", packet3_hdr, RADEON_CP_PACKET3 | RADEON_CP_NOP | (RELOC_SIZE << 16), reg);
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DRM_ERROR("Packet 3 was %x should have been %x: reg is %x at %d\n", packet3_hdr, RADEON_CP_PACKET3 | RADEON_CP_NOP | (RELOC_SIZE << 16), reg, offset_dw);
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return -EINVAL;
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}
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} else {
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if (packet3_hdr != (RADEON_CP_PACKET3 | RADEON_CP_NOP | (RELOC_SIZE_NEW << 16))) {
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DRM_ERROR("Packet 3 was %x should have been %x: reg is %x\n", packet3_hdr, RADEON_CP_PACKET3 | RADEON_CP_NOP | (RELOC_SIZE_NEW << 16), reg);
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DRM_ERROR("Packet 3 was %x should have been %x: reg is %x at %d\n", packet3_hdr, RADEON_CP_PACKET3 | RADEON_CP_NOP | (RELOC_SIZE_NEW << 16), reg, offset_dw);
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return -EINVAL;
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}
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@ -295,9 +293,11 @@ static __inline__ int radeon_cs_relocate_packet0(struct drm_radeon_cs_parser *pa
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case RADEON_DST_PITCH_OFFSET:
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case RADEON_SRC_PITCH_OFFSET:
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/* pass in the start of the reloc */
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ret = dev_priv->cs.relocate(parser, ib_chunk->kdata + offset_dw + 2, &offset);
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if (ret)
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ret = dev_priv->cs.relocate(parser,
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ib_chunk->kdata + offset_dw + 2, &offset);
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if (ret) {
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return ret;
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}
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tmp = (val & RADEON_2D_OFFSET_MASK) << 10;
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val &= ~RADEON_2D_OFFSET_MASK;
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offset += tmp;
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@ -313,9 +313,12 @@ static __inline__ int radeon_cs_relocate_packet0(struct drm_radeon_cs_parser *pa
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case R200_PP_TXOFFSET_1:
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case RADEON_PP_TXOFFSET_0:
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case RADEON_PP_TXOFFSET_1:
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ret = dev_priv->cs.relocate(parser, ib_chunk->kdata + offset_dw + 2, &offset);
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if (ret)
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ret = dev_priv->cs.relocate(parser,
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ib_chunk->kdata + offset_dw + 2, &offset);
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if (ret) {
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DRM_ERROR("Failed to relocate %d\n", offset_dw);
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return ret;
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}
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offset &= 0xffffffe0;
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val += offset;
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@ -332,8 +335,9 @@ static int radeon_cs_relocate_packet3(struct drm_radeon_cs_parser *parser,
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uint32_t offset_dw)
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{
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drm_radeon_private_t *dev_priv = parser->dev->dev_private;
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uint32_t hdr, num_dw, reg;
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uint32_t offset, val, tmp;
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uint32_t hdr, num_dw, reg, i;
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uint32_t offset, val, tmp, nptr, cptr;
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uint32_t *reloc;
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int ret;
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struct drm_radeon_kernel_chunk *ib_chunk;
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@ -347,11 +351,13 @@ static int radeon_cs_relocate_packet3(struct drm_radeon_cs_parser *parser,
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switch(reg) {
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case RADEON_CNTL_HOSTDATA_BLT:
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{
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val = ib_chunk->kdata[offset_dw + 2];
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ret = dev_priv->cs.relocate(parser, ib_chunk->kdata + offset_dw + num_dw + 2, &offset);
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if (ret)
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ret = dev_priv->cs.relocate(parser,
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ib_chunk->kdata + offset_dw + num_dw + 2,
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&offset);
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if (ret) {
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return ret;
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}
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tmp = (val & RADEON_2D_OFFSET_MASK) << 10;
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val &= ~RADEON_2D_OFFSET_MASK;
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@ -360,8 +366,48 @@ static int radeon_cs_relocate_packet3(struct drm_radeon_cs_parser *parser,
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val |= offset;
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ib_chunk->kdata[offset_dw + 2] = val;
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}
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break;
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case RADEON_3D_LOAD_VBPNTR:
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nptr = ib_chunk->kdata[offset_dw + 1];
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cptr = offset_dw + 3;
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for (i = 0; i < (nptr & ~1); i+= 2) {
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reloc = ib_chunk->kdata + offset_dw + num_dw + 2;
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reloc += ((i + 0) * 2);
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ret = dev_priv->cs.relocate(parser, reloc, &offset);
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if (ret) {
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return ret;
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}
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ib_chunk->kdata[cptr] += offset;
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cptr += 1;
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reloc = ib_chunk->kdata + offset_dw + num_dw + 2;
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reloc += ((i + 1) * 2);
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ret = dev_priv->cs.relocate(parser, reloc, &offset);
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if (ret) {
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return ret;
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}
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ib_chunk->kdata[cptr] += offset;
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cptr += 2;
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}
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if (nptr & 1) {
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reloc = ib_chunk->kdata + offset_dw + num_dw + 2;
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reloc += ((nptr - 1) * 2);
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ret = dev_priv->cs.relocate(parser, reloc, &offset);
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if (ret) {
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return ret;
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}
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ib_chunk->kdata[cptr] += offset;
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}
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break;
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case RADEON_CP_INDX_BUFFER:
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reloc = ib_chunk->kdata + offset_dw + num_dw + 2;
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ret = dev_priv->cs.relocate(parser, reloc, &offset);
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if (ret) {
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return ret;
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}
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ib_chunk->kdata[offset_dw + 2] += offset;
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break;
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default:
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DRM_ERROR("Unknown packet3 0x%08X\n", hdr);
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return -EINVAL;
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}
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return 0;
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@ -377,6 +423,12 @@ int radeon_cs_packet0(struct drm_radeon_cs_parser *parser, uint32_t offset_dw)
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num_dw = ((hdr & RADEON_CP_PACKET_COUNT_MASK) >> 16) + 2;
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reg = (hdr & R300_CP_PACKET0_REG_MASK) << 2;
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if (hdr & (1 << 15)) {
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if (reg == 0x2208) {
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return 0;
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}
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}
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while (count_dw < num_dw) {
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/* need to have something like the r300 validation here -
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list of allowed registers */
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@ -405,7 +457,8 @@ int radeon_cs_packet0(struct drm_radeon_cs_parser *parser, uint32_t offset_dw)
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} else if (flags == MARK_CHECK_SCISSOR) {
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DRM_DEBUG("need to validate scissor %x %d\n", reg, flags);
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} else {
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DRM_DEBUG("illegal register %x %d\n", reg, flags);
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DRM_ERROR("illegal register 0x%x %d at %d\n", reg, flags, offset_dw);
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return -EINVAL;
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}
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break;
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@ -435,6 +488,8 @@ int radeon_cs_parse(struct drm_radeon_cs_parser *parser)
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switch (hdr & RADEON_CP_PACKET_MASK) {
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case RADEON_CP_PACKET0:
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ret = radeon_cs_packet0(parser, count_dw);
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if (ret)
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return ret;
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break;
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case RADEON_CP_PACKET1:
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case RADEON_CP_PACKET2:
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@ -446,14 +501,17 @@ int radeon_cs_parse(struct drm_radeon_cs_parser *parser)
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reg = hdr & 0xff00;
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switch(reg) {
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case RADEON_3D_LOAD_VBPNTR:
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case RADEON_CP_INDX_BUFFER:
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case RADEON_CNTL_HOSTDATA_BLT:
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radeon_cs_relocate_packet3(parser, count_dw);
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ret =radeon_cs_relocate_packet3(parser,
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count_dw);
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if (ret)
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return ret;
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break;
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case RADEON_CNTL_BITBLT_MULTI:
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case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */
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case RADEON_CP_INDX_BUFFER:
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DRM_ERROR("need relocate packet 3 for %x\n", reg);
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DRM_ERROR("need relocate packet 3 for %x %d\n", reg, count_dw);
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break;
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case RADEON_3D_DRAW_IMMD: /* triggers drawing using in-packet vertex data */
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@ -464,12 +522,11 @@ int radeon_cs_parse(struct drm_radeon_cs_parser *parser)
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case RADEON_CP_NOP:
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break;
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default:
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DRM_ERROR("unknown packet 3 %x\n", reg);
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DRM_ERROR("unknown packet 3 %x at %d\n", reg, count_dw);
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ret = -EINVAL;
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}
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break;
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}
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count_dw += num_dw+2;
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}
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