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tests/amdgpu:retire asic_id check on unsupported cases 

Retire the asic_id check for AI family.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
main
Feifei Xu 2020-11-25 17:20:33 +08:00
parent 991e95fd13
commit 7b844dabf9
7 changed files with 78 additions and 34 deletions
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17
tests/amdgpu/amdgpu_test.h
View File

@ -449,13 +449,18 @@ static inline CU_ErrorCode amdgpu_set_test_active(const char *suite_name,
return r;
}
static inline bool asic_is_arcturus(uint32_t asic_id)
static inline bool asic_is_gfx_pipe_removed(uint32_t family_id, uint32_t chip_id, uint32_t chip_rev)
{
switch(asic_id) {
/* Arcturus asic DID */
case 0x738C:
case 0x7388:
case 0x738E:
if (family_id != AMDGPU_FAMILY_AI)
return false;
switch (chip_id - chip_rev) {
/* Arcturus */
case 0x32:
/* Aldebaran */
case 0x3c:
return true;
default:
return false;

37
tests/amdgpu/basic_tests.c
View File

@ -46,6 +46,8 @@ static amdgpu_device_handle device_handle;
static uint32_t major_version;
static uint32_t minor_version;
static uint32_t family_id;
static uint32_t chip_id;
static uint32_t chip_rev;
static void amdgpu_query_info_test(void);
static void amdgpu_command_submission_gfx(void);
@ -619,19 +621,20 @@ int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size,
CU_BOOL suite_basic_tests_enable(void)
{
uint32_t asic_id;
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
&minor_version, &device_handle))
return CU_FALSE;
asic_id = device_handle->info.asic_id;
if (amdgpu_device_deinitialize(device_handle))
return CU_FALSE;
/* disable gfx engine basic test cases for Arturus due to no CPG */
if (asic_is_arcturus(asic_id)) {
family_id = device_handle->info.family_id;
chip_id = device_handle->info.chip_external_rev;
chip_rev = device_handle->info.chip_rev;
/* disable gfx engine basic test cases for some asics have no CPG */
if (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) {
if (amdgpu_set_test_active("Basic Tests",
"Command submission Test (GFX)",
CU_FALSE))
@ -1073,6 +1076,14 @@ static void amdgpu_semaphore_test(void)
amdgpu_bo_list_handle bo_list[2];
amdgpu_va_handle va_handle[2];
int r, i;
struct amdgpu_gpu_info gpu_info = {0};
unsigned gc_ip_type;
r = amdgpu_query_gpu_info(device_handle, &gpu_info);
CU_ASSERT_EQUAL(r, 0);
gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ?
AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX;
if (family_id == AMDGPU_FAMILY_SI) {
sdma_nop = SDMA_PACKET_SI(SDMA_NOP_SI, 0, 0, 0, 0);
@ -1115,14 +1126,14 @@ static void amdgpu_semaphore_test(void)
r = amdgpu_cs_signal_semaphore(context_handle[0], AMDGPU_HW_IP_DMA, 0, 0, sem);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_cs_wait_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0, sem);
r = amdgpu_cs_wait_semaphore(context_handle[0], gc_ip_type, 0, 0, sem);
CU_ASSERT_EQUAL(r, 0);
ptr = ib_result_cpu[1];
ptr[0] = gfx_nop;
ib_info[1].ib_mc_address = ib_result_mc_address[1];
ib_info[1].size = 1;
ibs_request[1].ip_type = AMDGPU_HW_IP_GFX;
ibs_request[1].ip_type = gc_ip_type;
ibs_request[1].number_of_ibs = 1;
ibs_request[1].ibs = &ib_info[1];
ibs_request[1].resources = bo_list[1];
@ -1132,7 +1143,7 @@ static void amdgpu_semaphore_test(void)
CU_ASSERT_EQUAL(r, 0);
fence_status.context = context_handle[0];
fence_status.ip_type = AMDGPU_HW_IP_GFX;
fence_status.ip_type = gc_ip_type;
fence_status.ip_instance = 0;
fence_status.fence = ibs_request[1].seq_no;
r = amdgpu_cs_query_fence_status(&fence_status,
@ -1146,24 +1157,24 @@ static void amdgpu_semaphore_test(void)
ib_info[0].ib_mc_address = ib_result_mc_address[0];
ib_info[0].size = 1;
ibs_request[0].ip_type = AMDGPU_HW_IP_GFX;
ibs_request[0].ip_type = gc_ip_type;
ibs_request[0].number_of_ibs = 1;
ibs_request[0].ibs = &ib_info[0];
ibs_request[0].resources = bo_list[0];
ibs_request[0].fence_info.handle = NULL;
r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[0], 1);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_cs_signal_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0, sem);
r = amdgpu_cs_signal_semaphore(context_handle[0], gc_ip_type, 0, 0, sem);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_cs_wait_semaphore(context_handle[1], AMDGPU_HW_IP_GFX, 0, 0, sem);
r = amdgpu_cs_wait_semaphore(context_handle[1], gc_ip_type, 0, 0, sem);
CU_ASSERT_EQUAL(r, 0);
ptr = ib_result_cpu[1];
ptr[0] = gfx_nop;
ib_info[1].ib_mc_address = ib_result_mc_address[1];
ib_info[1].size = 1;
ibs_request[1].ip_type = AMDGPU_HW_IP_GFX;
ibs_request[1].ip_type = gc_ip_type;
ibs_request[1].number_of_ibs = 1;
ibs_request[1].ibs = &ib_info[1];
ibs_request[1].resources = bo_list[1];
@ -1173,7 +1184,7 @@ static void amdgpu_semaphore_test(void)
CU_ASSERT_EQUAL(r, 0);
fence_status.context = context_handle[1];
fence_status.ip_type = AMDGPU_HW_IP_GFX;
fence_status.ip_type = gc_ip_type;
fence_status.ip_instance = 0;
fence_status.fence = ibs_request[1].seq_no;
r = amdgpu_cs_query_fence_status(&fence_status,

7
tests/amdgpu/cs_tests.c
View File

@ -64,21 +64,20 @@ CU_TestInfo cs_tests[] = {
CU_BOOL suite_cs_tests_enable(void)
{
uint32_t asic_id;
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
&minor_version, &device_handle))
return CU_FALSE;
family_id = device_handle->info.family_id;
asic_id = device_handle->info.asic_id;
chip_id = device_handle->info.chip_external_rev;
chip_rev = device_handle->info.chip_rev;
if (amdgpu_device_deinitialize(device_handle))
return CU_FALSE;
if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI ||
asic_is_arcturus(asic_id)) {
asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) {
printf("\n\nThe ASIC NOT support UVD, suite disabled\n");
return CU_FALSE;
}

18
tests/amdgpu/deadlock_tests.c
View File

@ -106,6 +106,10 @@ static uint32_t minor_version;
static pthread_t stress_thread;
static uint32_t *ptr;
static uint32_t family_id;
static uint32_t chip_rev;
static uint32_t chip_id;
int use_uc_mtype = 0;
static void amdgpu_deadlock_helper(unsigned ip_type);
@ -124,25 +128,27 @@ static void amdgpu_draw_hang_slow_gfx(void);
CU_BOOL suite_deadlock_tests_enable(void)
{
CU_BOOL enable = CU_TRUE;
uint32_t asic_id;
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
&minor_version, &device_handle))
return CU_FALSE;
family_id = device_handle->info.family_id;
chip_id = device_handle->info.chip_external_rev;
chip_rev = device_handle->info.chip_rev;
/*
* Only enable for ASICs supporting GPU reset and for which it's enabled
* by default (currently GFX8/9 dGPUS)
*/
if (device_handle->info.family_id != AMDGPU_FAMILY_VI &&
device_handle->info.family_id != AMDGPU_FAMILY_AI &&
device_handle->info.family_id != AMDGPU_FAMILY_CI) {
if (family_id != AMDGPU_FAMILY_VI &&
family_id != AMDGPU_FAMILY_AI &&
family_id != AMDGPU_FAMILY_CI) {
printf("\n\nGPU reset is not enabled for the ASIC, deadlock suite disabled\n");
enable = CU_FALSE;
}
asic_id = device_handle->info.asic_id;
if (asic_is_arcturus(asic_id)) {
if (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) {
if (amdgpu_set_test_active("Deadlock Tests",
"gfx ring block test (set amdgpu.lockup_timeout=50)",
CU_FALSE))

22
tests/amdgpu/syncobj_tests.c
View File

@ -33,6 +33,10 @@ static amdgpu_device_handle device_handle;
static uint32_t major_version;
static uint32_t minor_version;
static uint32_t family_id;
static uint32_t chip_id;
static uint32_t chip_rev;
static void amdgpu_syncobj_timeline_test(void);
CU_BOOL suite_syncobj_timeline_tests_enable(void)
@ -99,7 +103,19 @@ static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool
uint32_t expired;
int i, r;
uint64_t seq_no;
uint32_t *ptr;
static uint32_t *ptr;
struct amdgpu_gpu_info gpu_info = {0};
unsigned gc_ip_type;
r = amdgpu_query_gpu_info(device_handle, &gpu_info);
CU_ASSERT_EQUAL(r, 0);
family_id = device_handle->info.family_id;
chip_id = device_handle->info.chip_external_rev;
chip_rev = device_handle->info.chip_rev;
gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ?
AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX;
r = amdgpu_cs_ctx_create(device_handle, &context_handle);
CU_ASSERT_EQUAL(r, 0);
@ -125,7 +141,7 @@ static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool
chunk_data.ib_data._pad = 0;
chunk_data.ib_data.va_start = ib_result_mc_address;
chunk_data.ib_data.ib_bytes = 16 * 4;
chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
chunk_data.ib_data.ip_type = wait_or_signal ? gc_ip_type :
AMDGPU_HW_IP_DMA;
chunk_data.ib_data.ip_instance = 0;
chunk_data.ib_data.ring = 0;
@ -151,7 +167,7 @@ static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool
memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
fence_status.context = context_handle;
fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
fence_status.ip_type = wait_or_signal ? gc_ip_type :
AMDGPU_HW_IP_DMA;
fence_status.ip_instance = 0;
fence_status.ring = 0;

2
tests/amdgpu/vce_tests.c
View File

@ -116,7 +116,7 @@ CU_BOOL suite_vce_tests_enable(void)
return CU_FALSE;
if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI ||
asic_is_arcturus(asic_id)) {
asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) {
printf("\n\nThe ASIC NOT support VCE, suite disabled\n");
return CU_FALSE;
}

9
tests/amdgpu/vm_tests.c
View File

@ -30,6 +30,9 @@
static amdgpu_device_handle device_handle;
static uint32_t major_version;
static uint32_t minor_version;
static uint32_t family_id;
static uint32_t chip_id;
static uint32_t chip_rev;
static void amdgpu_vmid_reserve_test(void);
static void amdgpu_vm_unaligned_map(void);
@ -110,7 +113,11 @@ static void amdgpu_vmid_reserve_test(void)
r = amdgpu_query_gpu_info(device_handle, &gpu_info);
CU_ASSERT_EQUAL(r, 0);
gc_ip_type = (asic_is_arcturus(gpu_info.asic_id)) ?
family_id = device_handle->info.family_id;
chip_id = device_handle->info.chip_external_rev;
chip_rev = device_handle->info.chip_rev;
gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ?
AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX;
r = amdgpu_cs_ctx_create(device_handle, &context_handle);