Still more work on the context switching code.
parent
a749d9d5b4
commit
7ef44b2b8d
|
@ -112,8 +112,6 @@ typedef struct drm_nouveau_private {
|
||||||
drm_local_map_t *mmio;
|
drm_local_map_t *mmio;
|
||||||
drm_local_map_t *fb;
|
drm_local_map_t *fb;
|
||||||
|
|
||||||
int64_t fb_usable_size;
|
|
||||||
|
|
||||||
int cur_fifo;
|
int cur_fifo;
|
||||||
|
|
||||||
struct nouveau_object *fb_obj;
|
struct nouveau_object *fb_obj;
|
||||||
|
|
|
@ -227,7 +227,7 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init,
|
||||||
/* disable the fifo caches */
|
/* disable the fifo caches */
|
||||||
NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
|
NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
|
||||||
|
|
||||||
if (dev_priv->card_type <= NV_04)
|
if (dev_priv->card_type <= NV_05)
|
||||||
ctx_size=32;
|
ctx_size=32;
|
||||||
else
|
else
|
||||||
ctx_size=128;
|
ctx_size=128;
|
||||||
|
@ -239,7 +239,7 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init,
|
||||||
|
|
||||||
NV_WRITE(ctx_addr,init->put_base);
|
NV_WRITE(ctx_addr,init->put_base);
|
||||||
NV_WRITE(ctx_addr+4,init->put_base);
|
NV_WRITE(ctx_addr+4,init->put_base);
|
||||||
if (dev_priv->card_type <= NV_04)
|
if (dev_priv->card_type <= NV_05)
|
||||||
{
|
{
|
||||||
// that's what is done in nvosdk, but that part of the code is buggy so...
|
// that's what is done in nvosdk, but that part of the code is buggy so...
|
||||||
NV_WRITE(ctx_addr+8,dev_priv->cmdbuf_obj->instance >> 4);
|
NV_WRITE(ctx_addr+8,dev_priv->cmdbuf_obj->instance >> 4);
|
||||||
|
|
|
@ -69,7 +69,15 @@ void nouveau_irq_postinstall(drm_device_t *dev)
|
||||||
DRM_DEBUG("IRQ: postinst\n");
|
DRM_DEBUG("IRQ: postinst\n");
|
||||||
|
|
||||||
/* Enable PFIFO error reporting */
|
/* Enable PFIFO error reporting */
|
||||||
NV_WRITE(NV_PFIFO_INTEN , NV_PFIFO_INTR_ERROR);
|
NV_WRITE(NV_PFIFO_INTEN ,
|
||||||
|
NV_PFIFO_INTR_CACHE_ERROR |
|
||||||
|
NV_PFIFO_INTR_RUNOUT |
|
||||||
|
NV_PFIFO_INTR_RUNOUT_OVERFLOW |
|
||||||
|
NV_PFIFO_INTR_DMA_PUSHER |
|
||||||
|
NV_PFIFO_INTR_DMA_PT |
|
||||||
|
NV_PFIFO_INTR_SEMAPHORE |
|
||||||
|
NV_PFIFO_INTR_ACQUIRE_TIMEOUT
|
||||||
|
);
|
||||||
NV_WRITE(NV_PFIFO_INTSTAT, 0xFFFFFFFF);
|
NV_WRITE(NV_PFIFO_INTSTAT, 0xFFFFFFFF);
|
||||||
|
|
||||||
/* Enable PGRAPH interrupts */
|
/* Enable PGRAPH interrupts */
|
||||||
|
@ -279,6 +287,7 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev)
|
||||||
switch(dev_priv->card_type)
|
switch(dev_priv->card_type)
|
||||||
{
|
{
|
||||||
case NV_04:
|
case NV_04:
|
||||||
|
case NV_05:
|
||||||
nouveau_nv04_context_switch(dev);
|
nouveau_nv04_context_switch(dev);
|
||||||
break;
|
break;
|
||||||
case NV_10:
|
case NV_10:
|
||||||
|
|
|
@ -75,7 +75,13 @@
|
||||||
#define NV_PFIFO_DMA_TIMESLICE 0x00002044
|
#define NV_PFIFO_DMA_TIMESLICE 0x00002044
|
||||||
#define NV_PFIFO_INTSTAT 0x00002100
|
#define NV_PFIFO_INTSTAT 0x00002100
|
||||||
#define NV_PFIFO_INTEN 0x00002140
|
#define NV_PFIFO_INTEN 0x00002140
|
||||||
# define NV_PFIFO_INTR_ERROR (1<<0)
|
# define NV_PFIFO_INTR_CACHE_ERROR (1<< 0)
|
||||||
|
# define NV_PFIFO_INTR_RUNOUT (1<< 4)
|
||||||
|
# define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<< 8)
|
||||||
|
# define NV_PFIFO_INTR_DMA_PUSHER (1<<12)
|
||||||
|
# define NV_PFIFO_INTR_DMA_PT (1<<16)
|
||||||
|
# define NV_PFIFO_INTR_SEMAPHORE (1<<20)
|
||||||
|
# define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24)
|
||||||
#define NV_PFIFO_RAMHT 0x00002210
|
#define NV_PFIFO_RAMHT 0x00002210
|
||||||
#define NV_PFIFO_RAMFC 0x00002214
|
#define NV_PFIFO_RAMFC 0x00002214
|
||||||
#define NV_PFIFO_RAMRO 0x00002218
|
#define NV_PFIFO_RAMRO 0x00002218
|
||||||
|
@ -91,7 +97,6 @@
|
||||||
#define NV_PFIFO_CACH1_DMAPSH 0x00003220
|
#define NV_PFIFO_CACH1_DMAPSH 0x00003220
|
||||||
#define NV_PFIFO_CACH1_DMAF 0x00003224
|
#define NV_PFIFO_CACH1_DMAF 0x00003224
|
||||||
# define NV_PFIFO_CACH1_DMAF_TRIG_8_BYTES 0x00000000
|
# define NV_PFIFO_CACH1_DMAF_TRIG_8_BYTES 0x00000000
|
||||||
# define NV_PFIFO_CACH1_DMAF_TRIG_8_BYTES 0x00000000
|
|
||||||
# define NV_PFIFO_CACH1_DMAF_TRIG_16_BYTES 0x00000008
|
# define NV_PFIFO_CACH1_DMAF_TRIG_16_BYTES 0x00000008
|
||||||
# define NV_PFIFO_CACH1_DMAF_TRIG_24_BYTES 0x00000010
|
# define NV_PFIFO_CACH1_DMAF_TRIG_24_BYTES 0x00000010
|
||||||
# define NV_PFIFO_CACH1_DMAF_TRIG_32_BYTES 0x00000018
|
# define NV_PFIFO_CACH1_DMAF_TRIG_32_BYTES 0x00000018
|
||||||
|
|
|
@ -64,11 +64,6 @@ int nouveau_firstopen(struct drm_device *dev)
|
||||||
|
|
||||||
DRM_INFO("%lld MB of video ram detected\n",nouveau_mem_fb_amount(dev)>>20);
|
DRM_INFO("%lld MB of video ram detected\n",nouveau_mem_fb_amount(dev)>>20);
|
||||||
|
|
||||||
if (dev_priv->card_type>=NV_40)
|
|
||||||
dev_priv->fb_usable_size=nouveau_mem_fb_amount(dev)-560*1024;
|
|
||||||
else
|
|
||||||
dev_priv->fb_usable_size=nouveau_mem_fb_amount(dev)-256*1024;
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue