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Use lowercase bool constants.

main
Kristian Høgsberg 2008-07-07 11:56:59 -04:00
parent f58e21c7d0
commit 7fd8a5de63
13 changed files with 97 additions and 96 deletions
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1
linux-core/drmP.h
View File

@ -54,6 +54,7 @@
#include <linux/smp_lock.h> /* For (un)lock_kernel */
#include <linux/dma-mapping.h>
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/kref.h>
#include <linux/pagemap.h>
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,16)

6
linux-core/drm_agpsupport.c
View File

@ -517,7 +517,7 @@ drm_agp_bind_pages(struct drm_device *dev,
mem->memory[i] = phys_to_gart(page_to_phys(pages[i]));
mem->page_count = num_pages;
mem->is_flushed = TRUE;
mem->is_flushed = true;
ret = drm_agp_bind_memory(mem, gtt_offset / PAGE_SIZE);
if (ret != 0) {
DRM_ERROR("Failed to bind AGP memory: %d\n", ret);
@ -597,7 +597,7 @@ static int drm_agp_bind_ttm(struct drm_ttm_backend *backend,
int snooped = (bo_mem->flags & DRM_BO_FLAG_CACHED) && !(bo_mem->flags & DRM_BO_FLAG_CACHED_MAPPED);
DRM_DEBUG("drm_agp_bind_ttm\n");
mem->is_flushed = TRUE;
mem->is_flushed = true;
mem->type = AGP_USER_MEMORY;
/* CACHED MAPPED implies not snooped memory */
if (snooped)
@ -696,7 +696,7 @@ struct drm_ttm_backend *drm_agp_init_ttm(struct drm_device *dev)
agp_be->mem = NULL;
agp_be->bridge = dev->agp->bridge;
agp_be->populated = FALSE;
agp_be->populated = false;
agp_be->backend.func = &agp_ttm_backend;
agp_be->backend.dev = dev;

2
linux-core/drm_crtc_helper.c
View File

@ -95,7 +95,7 @@ void drm_helper_probe_single_connector_modes(struct drm_connector *connector, ui
}
drm_mode_prune_invalid(dev, &connector->modes, TRUE);
drm_mode_prune_invalid(dev, &connector->modes, true);
if (list_empty(&connector->modes)) {
struct drm_display_mode *stdmode;

2
linux-core/dvo_ch7xxx.c
View File

@ -221,7 +221,7 @@ static bool ch7xxx_init(struct intel_dvo_device *dvo,
goto out;
}
ch7xxx->quiet = FALSE;
ch7xxx->quiet = false;
DRM_DEBUG("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n",
name, vendor, device);
return true;

2
linux-core/dvo_ivch.c
View File

@ -265,7 +265,7 @@ static bool ivch_init(struct intel_dvo_device *dvo,
dvo->i2c_bus = i2cbus;
dvo->i2c_bus->slave_addr = dvo->slave_addr;
dvo->dev_priv = priv;
priv->quiet = TRUE;
priv->quiet = true;
if (!ivch_read(dvo, VR00, &temp))
goto out;

4
linux-core/dvo_tfp410.c
View File

@ -187,7 +187,7 @@ static bool tfp410_init(struct intel_dvo_device *dvo,
dvo->i2c_bus = i2cbus;
dvo->i2c_bus->slave_addr = dvo->slave_addr;
dvo->dev_priv = tfp;
tfp->quiet = TRUE;
tfp->quiet = true;
if ((id = tfp410_getid(dvo, TFP410_VID_LO)) != TFP410_VID) {
DRM_DEBUG("tfp410 not detected got VID %X: from %s Slave %d.\n",
@ -200,7 +200,7 @@ static bool tfp410_init(struct intel_dvo_device *dvo,
id, i2cbus->adapter.name, i2cbus->slave_addr);
goto out;
}
tfp->quiet = FALSE;
tfp->quiet = false;
return true;
out:
kfree(tfp);

4
linux-core/intel_crt.c
View File

@ -136,8 +136,8 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
*
* Not for i915G/i915GM
*
* \return TRUE if CRT is connected.
* \return FALSE if CRT is disconnected.
* \return true if CRT is connected.
* \return false if CRT is disconnected.
*/
static bool intel_crt_detect_hotplug(struct drm_connector *connector)
{

16
linux-core/intel_display.c
View File

@ -510,7 +510,7 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
intel_crtc_load_lut(crtc);
/* Give the overlay scaler a chance to enable if it's on this pipe */
//intel_crtc_dpms_video(crtc, TRUE); TODO
//intel_crtc_dpms_video(crtc, true); TODO
break;
case DPMSModeOff:
/* Give the overlay scaler a chance to disable if it's on this pipe */
@ -737,19 +737,19 @@ static void intel_crtc_mode_set(struct drm_crtc *crtc,
switch (intel_output->type) {
case INTEL_OUTPUT_LVDS:
is_lvds = TRUE;
is_lvds = true;
break;
case INTEL_OUTPUT_SDVO:
is_sdvo = TRUE;
is_sdvo = true;
break;
case INTEL_OUTPUT_DVO:
is_dvo = TRUE;
is_dvo = true;
break;
case INTEL_OUTPUT_TVOUT:
is_tv = TRUE;
is_tv = true;
break;
case INTEL_OUTPUT_ANALOG:
is_crt = TRUE;
is_crt = true;
break;
}
}
@ -1177,7 +1177,7 @@ struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
}
encoder->crtc = crtc;
intel_output->load_detect_temp = TRUE;
intel_output->load_detect_temp = true;
intel_crtc = to_intel_crtc(crtc);
*dpms_mode = intel_crtc->dpms_mode;
@ -1212,7 +1212,7 @@ void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_
if (intel_output->load_detect_temp) {
encoder->crtc = NULL;
intel_output->load_detect_temp = FALSE;
intel_output->load_detect_temp = false;
crtc->enabled = drm_helper_crtc_in_use(crtc);
drm_helper_disable_unused_functions(dev);
}

4
linux-core/intel_lvds.c
View File

@ -407,8 +407,8 @@ void intel_lvds_init(struct drm_device *dev)
drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
connector->display_info.subpixel_order = SubPixelHorizontalRGB;
connector->interlace_allowed = FALSE;
connector->doublescan_allowed = FALSE;
connector->interlace_allowed = false;
connector->doublescan_allowed = false;
/*

116
linux-core/intel_tv.c
View File

@ -422,18 +422,18 @@ const static struct tv_mode tv_modes[] = {
.hsync_end = 64, .hblank_end = 124,
.hblank_start = 836, .htotal = 857,
.progressive = FALSE, .trilevel_sync = FALSE,
.progressive = false, .trilevel_sync = false,
.vsync_start_f1 = 6, .vsync_start_f2 = 7,
.vsync_len = 6,
.veq_ena = TRUE, .veq_start_f1 = 0,
.veq_ena = true, .veq_start_f1 = 0,
.veq_start_f2 = 1, .veq_len = 18,
.vi_end_f1 = 20, .vi_end_f2 = 21,
.nbr_end = 240,
.burst_ena = TRUE,
.burst_ena = true,
.hburst_start = 72, .hburst_len = 34,
.vburst_start_f1 = 9, .vburst_end_f1 = 240,
.vburst_start_f2 = 10, .vburst_end_f2 = 240,
@ -445,7 +445,7 @@ const static struct tv_mode tv_modes[] = {
.dda2_inc = 7624, .dda2_size = 20013,
.dda3_inc = 0, .dda3_size = 0,
.sc_reset = TV_SC_RESET_EVERY_4,
.pal_burst = FALSE,
.pal_burst = false,
.composite_levels = &ntsc_m_levels_composite,
.composite_color = &ntsc_m_csc_composite,
@ -464,12 +464,12 @@ const static struct tv_mode tv_modes[] = {
.hsync_end = 64, .hblank_end = 124,
.hblank_start = 836, .htotal = 857,
.progressive = FALSE, .trilevel_sync = FALSE,
.progressive = false, .trilevel_sync = false,
.vsync_start_f1 = 6, .vsync_start_f2 = 7,
.vsync_len = 6,
.veq_ena = TRUE, .veq_start_f1 = 0,
.veq_ena = true, .veq_start_f1 = 0,
.veq_start_f2 = 1, .veq_len = 18,
.vi_end_f1 = 20, .vi_end_f2 = 21,
@ -487,7 +487,7 @@ const static struct tv_mode tv_modes[] = {
.dda2_inc = 18557, .dda2_size = 20625,
.dda3_inc = 0, .dda3_size = 0,
.sc_reset = TV_SC_RESET_EVERY_8,
.pal_burst = TRUE,
.pal_burst = true,
.composite_levels = &ntsc_m_levels_composite,
.composite_color = &ntsc_m_csc_composite,
@ -507,18 +507,18 @@ const static struct tv_mode tv_modes[] = {
.hsync_end = 64, .hblank_end = 124,
.hblank_start = 836, .htotal = 857,
.progressive = FALSE, .trilevel_sync = FALSE,
.progressive = false, .trilevel_sync = false,
.vsync_start_f1 = 6, .vsync_start_f2 = 7,
.vsync_len = 6,
.veq_ena = TRUE, .veq_start_f1 = 0,
.veq_ena = true, .veq_start_f1 = 0,
.veq_start_f2 = 1, .veq_len = 18,
.vi_end_f1 = 20, .vi_end_f2 = 21,
.nbr_end = 240,
.burst_ena = TRUE,
.burst_ena = true,
.hburst_start = 72, .hburst_len = 34,
.vburst_start_f1 = 9, .vburst_end_f1 = 240,
.vburst_start_f2 = 10, .vburst_end_f2 = 240,
@ -530,7 +530,7 @@ const static struct tv_mode tv_modes[] = {
.dda2_inc = 7624, .dda2_size = 20013,
.dda3_inc = 0, .dda3_size = 0,
.sc_reset = TV_SC_RESET_EVERY_4,
.pal_burst = FALSE,
.pal_burst = false,
.composite_levels = &ntsc_j_levels_composite,
.composite_color = &ntsc_j_csc_composite,
@ -550,18 +550,18 @@ const static struct tv_mode tv_modes[] = {
.hsync_end = 64, .hblank_end = 124,
.hblank_start = 836, .htotal = 857,
.progressive = FALSE, .trilevel_sync = FALSE,
.progressive = false, .trilevel_sync = false,
.vsync_start_f1 = 6, .vsync_start_f2 = 7,
.vsync_len = 6,
.veq_ena = TRUE, .veq_start_f1 = 0,
.veq_ena = true, .veq_start_f1 = 0,
.veq_start_f2 = 1, .veq_len = 18,
.vi_end_f1 = 20, .vi_end_f2 = 21,
.nbr_end = 240,
.burst_ena = TRUE,
.burst_ena = true,
.hburst_start = 72, .hburst_len = 34,
.vburst_start_f1 = 9, .vburst_end_f1 = 240,
.vburst_start_f2 = 10, .vburst_end_f2 = 240,
@ -573,7 +573,7 @@ const static struct tv_mode tv_modes[] = {
.dda2_inc = 7624, .dda2_size = 20013,
.dda3_inc = 0, .dda3_size = 0,
.sc_reset = TV_SC_RESET_EVERY_4,
.pal_burst = FALSE,
.pal_burst = false,
.composite_levels = &pal_m_levels_composite,
.composite_color = &pal_m_csc_composite,
@ -593,19 +593,19 @@ const static struct tv_mode tv_modes[] = {
.hsync_end = 64, .hblank_end = 128,
.hblank_start = 844, .htotal = 863,
.progressive = FALSE, .trilevel_sync = FALSE,
.progressive = false, .trilevel_sync = false,
.vsync_start_f1 = 6, .vsync_start_f2 = 7,
.vsync_len = 6,
.veq_ena = TRUE, .veq_start_f1 = 0,
.veq_ena = true, .veq_start_f1 = 0,
.veq_start_f2 = 1, .veq_len = 18,
.vi_end_f1 = 24, .vi_end_f2 = 25,
.nbr_end = 286,
.burst_ena = TRUE,
.burst_ena = true,
.hburst_start = 73, .hburst_len = 34,
.vburst_start_f1 = 8, .vburst_end_f1 = 285,
.vburst_start_f2 = 8, .vburst_end_f2 = 286,
@ -618,7 +618,7 @@ const static struct tv_mode tv_modes[] = {
.dda2_inc = 18557, .dda2_size = 20625,
.dda3_inc = 0, .dda3_size = 0,
.sc_reset = TV_SC_RESET_EVERY_8,
.pal_burst = TRUE,
.pal_burst = true,
.composite_levels = &pal_n_levels_composite,
.composite_color = &pal_n_csc_composite,
@ -638,18 +638,18 @@ const static struct tv_mode tv_modes[] = {
.hsync_end = 64, .hblank_end = 128,
.hblank_start = 844, .htotal = 863,
.progressive = FALSE, .trilevel_sync = FALSE,
.progressive = false, .trilevel_sync = false,
.vsync_start_f1 = 5, .vsync_start_f2 = 6,
.vsync_len = 5,
.veq_ena = TRUE, .veq_start_f1 = 0,
.veq_ena = true, .veq_start_f1 = 0,
.veq_start_f2 = 1, .veq_len = 15,
.vi_end_f1 = 24, .vi_end_f2 = 25,
.nbr_end = 286,
.burst_ena = TRUE,
.burst_ena = true,
.hburst_start = 73, .hburst_len = 32,
.vburst_start_f1 = 8, .vburst_end_f1 = 285,
.vburst_start_f2 = 8, .vburst_end_f2 = 286,
@ -661,7 +661,7 @@ const static struct tv_mode tv_modes[] = {
.dda2_inc = 18557, .dda2_size = 20625,
.dda3_inc = 0, .dda3_size = 0,
.sc_reset = TV_SC_RESET_EVERY_8,
.pal_burst = TRUE,
.pal_burst = true,
.composite_levels = &pal_levels_composite,
.composite_color = &pal_csc_composite,
@ -680,17 +680,17 @@ const static struct tv_mode tv_modes[] = {
.hsync_end = 64, .hblank_end = 122,
.hblank_start = 842, .htotal = 857,
.progressive = TRUE,.trilevel_sync = FALSE,
.progressive = true,.trilevel_sync = false,
.vsync_start_f1 = 12, .vsync_start_f2 = 12,
.vsync_len = 12,
.veq_ena = FALSE,
.veq_ena = false,
.vi_end_f1 = 44, .vi_end_f2 = 44,
.nbr_end = 496,
.burst_ena = FALSE,
.burst_ena = false,
.filter_table = filter_table,
},
@ -704,17 +704,17 @@ const static struct tv_mode tv_modes[] = {
.hsync_end = 64, .hblank_end = 122,
.hblank_start = 842, .htotal = 856,
.progressive = TRUE,.trilevel_sync = FALSE,
.progressive = true,.trilevel_sync = false,
.vsync_start_f1 = 12, .vsync_start_f2 = 12,
.vsync_len = 12,
.veq_ena = FALSE,
.veq_ena = false,
.vi_end_f1 = 44, .vi_end_f2 = 44,
.nbr_end = 496,
.burst_ena = FALSE,
.burst_ena = false,
.filter_table = filter_table,
},
@ -728,17 +728,17 @@ const static struct tv_mode tv_modes[] = {
.hsync_end = 64, .hblank_end = 139,
.hblank_start = 859, .htotal = 863,
.progressive = TRUE, .trilevel_sync = FALSE,
.progressive = true, .trilevel_sync = false,
.vsync_start_f1 = 10, .vsync_start_f2 = 10,
.vsync_len = 10,
.veq_ena = FALSE,
.veq_ena = false,
.vi_end_f1 = 48, .vi_end_f2 = 48,
.nbr_end = 575,
.burst_ena = FALSE,
.burst_ena = false,
.filter_table = filter_table,
},
@ -752,17 +752,17 @@ const static struct tv_mode tv_modes[] = {
.hsync_end = 80, .hblank_end = 300,
.hblank_start = 1580, .htotal = 1649,
.progressive = TRUE, .trilevel_sync = TRUE,
.progressive = true, .trilevel_sync = true,
.vsync_start_f1 = 10, .vsync_start_f2 = 10,
.vsync_len = 10,
.veq_ena = FALSE,
.veq_ena = false,
.vi_end_f1 = 29, .vi_end_f2 = 29,
.nbr_end = 719,
.burst_ena = FALSE,
.burst_ena = false,
.filter_table = filter_table,
},
@ -776,17 +776,17 @@ const static struct tv_mode tv_modes[] = {
.hsync_end = 80, .hblank_end = 300,
.hblank_start = 1580, .htotal = 1651,
.progressive = TRUE, .trilevel_sync = TRUE,
.progressive = true, .trilevel_sync = true,
.vsync_start_f1 = 10, .vsync_start_f2 = 10,
.vsync_len = 10,
.veq_ena = FALSE,
.veq_ena = false,
.vi_end_f1 = 29, .vi_end_f2 = 29,
.nbr_end = 719,
.burst_ena = FALSE,
.burst_ena = false,
.filter_table = filter_table,
},
@ -800,17 +800,17 @@ const static struct tv_mode tv_modes[] = {
.hsync_end = 80, .hblank_end = 300,
.hblank_start = 1580, .htotal = 1979,
.progressive = TRUE, .trilevel_sync = TRUE,
.progressive = true, .trilevel_sync = true,
.vsync_start_f1 = 10, .vsync_start_f2 = 10,
.vsync_len = 10,
.veq_ena = FALSE,
.veq_ena = false,
.vi_end_f1 = 29, .vi_end_f2 = 29,
.nbr_end = 719,
.burst_ena = FALSE,
.burst_ena = false,
.filter_table = filter_table,
.max_srcw = 800
@ -825,19 +825,19 @@ const static struct tv_mode tv_modes[] = {
.hsync_end = 88, .hblank_end = 235,
.hblank_start = 2155, .htotal = 2639,
.progressive = FALSE, .trilevel_sync = TRUE,
.progressive = false, .trilevel_sync = true,
.vsync_start_f1 = 4, .vsync_start_f2 = 5,
.vsync_len = 10,
.veq_ena = TRUE, .veq_start_f1 = 4,
.veq_ena = true, .veq_start_f1 = 4,
.veq_start_f2 = 4, .veq_len = 10,
.vi_end_f1 = 21, .vi_end_f2 = 22,
.nbr_end = 539,
.burst_ena = FALSE,
.burst_ena = false,
.filter_table = filter_table,
},
@ -851,19 +851,19 @@ const static struct tv_mode tv_modes[] = {
.hsync_end = 88, .hblank_end = 235,
.hblank_start = 2155, .htotal = 2199,
.progressive = FALSE, .trilevel_sync = TRUE,
.progressive = false, .trilevel_sync = true,
.vsync_start_f1 = 4, .vsync_start_f2 = 5,
.vsync_len = 10,
.veq_ena = TRUE, .veq_start_f1 = 4,
.veq_ena = true, .veq_start_f1 = 4,
.veq_start_f2 = 4, .veq_len = 10,
.vi_end_f1 = 21, .vi_end_f2 = 22,
.nbr_end = 539,
.burst_ena = FALSE,
.burst_ena = false,
.filter_table = filter_table,
},
@ -877,19 +877,19 @@ const static struct tv_mode tv_modes[] = {
.hsync_end = 88, .hblank_end = 235,
.hblank_start = 2155, .htotal = 2200,
.progressive = FALSE, .trilevel_sync = TRUE,
.progressive = false, .trilevel_sync = true,
.vsync_start_f1 = 4, .vsync_start_f2 = 5,
.vsync_len = 10,
.veq_ena = TRUE, .veq_start_f1 = 4,
.veq_ena = true, .veq_start_f1 = 4,
.veq_start_f2 = 4, .veq_len = 10,
.vi_end_f1 = 21, .vi_end_f2 = 22,
.nbr_end = 539,
.burst_ena = FALSE,
.burst_ena = false,
.filter_table = filter_table,
},
@ -1098,17 +1098,17 @@ intel_tv_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
struct drm_encoder *other_encoder;
if (!tv_mode)
return FALSE;
return false;
/* FIXME: lock encoder list */
list_for_each_entry(other_encoder, &drm_config->encoder_list, head) {
if (other_encoder != encoder &&
other_encoder->crtc == encoder->crtc)
return FALSE;
return false;
}
adjusted_mode->clock = tv_mode->clock;
return TRUE;
return true;
}
static void
@ -1152,7 +1152,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
color_conversion = &sdtv_csc_yprpb;
else
color_conversion = &hdtv_csc_yprpb;
burst_ena = FALSE;
burst_ena = false;
break;
case DRM_MODE_CONNECTOR_SVIDEO:
tv_ctl |= TV_ENC_OUTPUT_SVIDEO;
@ -1352,8 +1352,8 @@ static const struct drm_display_mode reported_modes[] = {
*
* Requires that the current pipe's DPLL is active.
* \return TRUE if TV is connected.
* \return FALSE if TV is disconnected.
* \return true if TV is connected.
* \return false if TV is disconnected.
*/
static int
intel_tv_detect_type (struct drm_crtc *crtc, struct intel_output *intel_output)
@ -1703,8 +1703,8 @@ intel_tv_init(struct drm_device *dev)
drm_encoder_helper_add(&intel_output->enc, &intel_tv_helper_funcs);
drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs);
connector->interlace_allowed = FALSE;
connector->doublescan_allowed = FALSE;
connector->interlace_allowed = false;
connector->doublescan_allowed = false;
/* Create TV properties then attach current values */
tv_format_names = drm_alloc(sizeof(char *) * NUM_TV_MODES,

6
linux-core/xgi_cmdlist.c
View File

@ -135,7 +135,7 @@ int xgi_submit_cmdlist(struct drm_device * dev, void * data,
DRM_DEBUG("info->cmdring.last_ptr != NULL\n");
if (pCmdInfo->type == BTYPE_3D) {
xgi_emit_flush(info, FALSE);
xgi_emit_flush(info, false);
}
info->cmdring.last_ptr[1] = cpu_to_le32(begin[1]);
@ -214,7 +214,7 @@ void xgi_cmdlist_cleanup(struct xgi_info * info)
* list chain with a flush command.
*/
if (info->cmdring.last_ptr != NULL) {
xgi_emit_flush(info, FALSE);
xgi_emit_flush(info, false);
xgi_emit_nop(info);
}
@ -322,5 +322,5 @@ void xgi_emit_irq(struct xgi_info * info)
if (info->cmdring.last_ptr == NULL)
return;
xgi_emit_flush(info, TRUE);
xgi_emit_flush(info, true);
}

4
linux-core/xgi_drv.c
View File

@ -307,8 +307,8 @@ void xgi_driver_lastclose(struct drm_device * dev)
|| info->pcie_heap_initialized) {
drm_sman_cleanup(&info->sman);
info->fb_heap_initialized = FALSE;
info->pcie_heap_initialized = FALSE;
info->fb_heap_initialized = false;
info->pcie_heap_initialized = false;
}
}
}

26
linux-core/xgi_misc.c
View File

@ -46,41 +46,41 @@ static bool xgi_validate_signal(struct drm_map * map)
check = le16_to_cpu(DRM_READ16(map, 0x2360));
if ((check & 0x3f) != ((check & 0x3f00) >> 8)) {
return FALSE;
return false;
}
/* Check RO channel */
DRM_WRITE8(map, 0x235c, 0x83);
check = le16_to_cpu(DRM_READ16(map, 0x2360));
if ((check & 0x0f) != ((check & 0xf0) >> 4)) {
return FALSE;
return false;
}
/* Check RW channel */
DRM_WRITE8(map, 0x235c, 0x88);
check = le16_to_cpu(DRM_READ16(map, 0x2360));
if ((check & 0x0f) != ((check & 0xf0) >> 4)) {
return FALSE;
return false;
}
/* Check RO channel outstanding */
DRM_WRITE8(map, 0x235c, 0x8f);
check = le16_to_cpu(DRM_READ16(map, 0x2360));
if (0 != (check & 0x3ff)) {
return FALSE;
return false;
}
/* Check RW channel outstanding */
DRM_WRITE8(map, 0x235c, 0x90);
check = le16_to_cpu(DRM_READ16(map, 0x2360));
if (0 != (check & 0x3ff)) {
return FALSE;
return false;
}
/* No pending PCIE request. GE stall. */
}
return TRUE;
return true;
}
@ -138,7 +138,7 @@ static void xgi_ge_hang_reset(struct drm_map * map)
bool xgi_ge_irq_handler(struct xgi_info * info)
{
const u32 int_status = le32_to_cpu(DRM_READ32(info->mmio_map, 0x2810));
bool is_support_auto_reset = FALSE;
bool is_support_auto_reset = false;
/* Check GE on/off */
if (0 == (0xffffc0f0 & int_status)) {
@ -179,15 +179,15 @@ bool xgi_ge_irq_handler(struct xgi_info * info)
cpu_to_le32((int_status & ~0x01) | 0x04000000));
}
return TRUE;
return true;
}
return FALSE;
return false;
}
bool xgi_crt_irq_handler(struct xgi_info * info)
{
bool ret = FALSE;
bool ret = false;
u8 save_3ce = DRM_READ8(info->mmio_map, 0x3ce);
/* CRT1 interrupt just happened
@ -205,7 +205,7 @@ bool xgi_crt_irq_handler(struct xgi_info * info)
op3cf_3d = IN3CFB(info->mmio_map, 0x3d);
OUT3CFB(info->mmio_map, 0x3d, (op3cf_3d | 0x04));
OUT3CFB(info->mmio_map, 0x3d, (op3cf_3d & ~0x04));
ret = TRUE;
ret = true;
}
DRM_WRITE8(info->mmio_map, 0x3ce, save_3ce);
@ -214,7 +214,7 @@ bool xgi_crt_irq_handler(struct xgi_info * info)
bool xgi_dvi_irq_handler(struct xgi_info * info)
{
bool ret = FALSE;
bool ret = false;
const u8 save_3ce = DRM_READ8(info->mmio_map, 0x3ce);
/* DVI interrupt just happened
@ -242,7 +242,7 @@ bool xgi_dvi_irq_handler(struct xgi_info * info)
OUT3C5B(info->mmio_map, 0x39, (op3cf_39 & ~0x01));
OUT3C5B(info->mmio_map, 0x39, (op3cf_39 | 0x01));
ret = TRUE;
ret = true;
}
DRM_WRITE8(info->mmio_map, 0x3ce, save_3ce);