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amdgpu: Use new suite/test disabling functionality. 

Switch from disabling tests during run to using the new disable
API.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
main
Andrey Grodzovsky 2017-11-09 23:30:01 -05:00 committed by Christian König
parent 864219425d
commit 806d080360
6 changed files with 120 additions and 131 deletions
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14
tests/amdgpu/amdgpu_test.c
View File

@ -150,15 +150,15 @@ static Suites_Active_Status suites_active_stat[] = {
},
{
.pName = VCE_TESTS_STR,
.pActive = always_active,
.pActive = suite_vce_tests_enable,
},
{
.pName = VCN_TESTS_STR,
.pActive = always_active,
.pActive = suite_vcn_tests_enable,
},
{
.pName = UVD_ENC_TESTS_STR,
.pActive = always_active,
.pActive = suite_uvd_enc_tests_enable,
},
{
.pName = DEADLOCK_TESTS_STR,
@ -409,6 +409,14 @@ static void amdgpu_disable_suits()
if (amdgpu_set_suite_active(suites_active_stat[i].pName,
suites_active_stat[i].pActive()))
fprintf(stderr, "suit deactivation failed - %s\n", CU_get_error_msg());
/* Explicitly disable specific tests due to known bugs or preferences */
/*
* BUG: Compute ring stalls and never recovers when the address is
* written after the command already submitted
*/
if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, "compute ring block test", CU_FALSE))
fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
}
/* The main() function for setting up and running the tests.

15
tests/amdgpu/amdgpu_test.h
View File

@ -99,6 +99,11 @@ int suite_vce_tests_init();
*/
int suite_vce_tests_clean();
/**
* Decide if the suite is enabled by default or not.
*/
CU_BOOL suite_vce_tests_enable(void);
/**
* Tests in vce test suite
*/
@ -114,6 +119,11 @@ int suite_vcn_tests_init();
+ */
int suite_vcn_tests_clean();
/**
* Decide if the suite is enabled by default or not.
*/
CU_BOOL suite_vcn_tests_enable(void);
/**
+ * Tests in vcn test suite
+ */
@ -129,6 +139,11 @@ int suite_uvd_enc_tests_init();
*/
int suite_uvd_enc_tests_clean();
/**
* Decide if the suite is enabled by default or not.
*/
CU_BOOL suite_uvd_enc_tests_enable(void);
/**
* Tests in uvd enc test suite
*/

8
tests/amdgpu/deadlock_tests.c
View File

@ -119,13 +119,7 @@ int suite_deadlock_tests_clean(void)
CU_TestInfo deadlock_tests[] = {
{ "gfx ring block test", amdgpu_deadlock_gfx },
/*
* BUG: Compute ring stalls and never recovers when the address is
* written after the command already submitted
*/
/* { "compute ring block test", amdgpu_deadlock_compute }, */
{ "compute ring block test", amdgpu_deadlock_compute },
CU_TEST_INFO_NULL,
};

81
tests/amdgpu/uvd_enc_tests.c
View File

@ -79,7 +79,6 @@ static void amdgpu_cs_uvd_enc_session_init(void);
static void amdgpu_cs_uvd_enc_encode(void);
static void amdgpu_cs_uvd_enc_destroy(void);
static bool uvd_enc_support(void);
CU_TestInfo uvd_enc_tests[] = {
{ "UVD ENC create", amdgpu_cs_uvd_enc_create },
@ -89,6 +88,27 @@ CU_TestInfo uvd_enc_tests[] = {
CU_TEST_INFO_NULL,
};
CU_BOOL suite_uvd_enc_tests_enable(void)
{
int r;
struct drm_amdgpu_info_hw_ip info;
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
&minor_version, &device_handle))
return CU_FALSE;
r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_UVD_ENC, 0, &info);
if (amdgpu_device_deinitialize(device_handle))
return CU_FALSE;
if (!info.available_rings)
printf("\n\nThe ASIC NOT support UVD ENC, suite disabled.\n");
return (r == 0 && (info.available_rings ? CU_TRUE : CU_FALSE));
}
int suite_uvd_enc_tests_init(void)
{
int r;
@ -100,11 +120,6 @@ int suite_uvd_enc_tests_init(void)
family_id = device_handle->info.family_id;
if (!uvd_enc_support()) {
printf("\n\nThe ASIC NOT support UVD ENC, all sub-tests will pass\n");
return CUE_SUCCESS;
}
r = amdgpu_cs_ctx_create(device_handle, &context_handle);
if (r)
return CUE_SINIT_FAILED;
@ -123,28 +138,18 @@ int suite_uvd_enc_tests_clean(void)
{
int r;
if (!uvd_enc_support()) {
r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
ib_mc_address, IB_SIZE);
if (r)
return CUE_SCLEAN_FAILED;
r = amdgpu_device_deinitialize(device_handle);
if (r)
return CUE_SCLEAN_FAILED;
r = amdgpu_cs_ctx_free(context_handle);
if (r)
return CUE_SCLEAN_FAILED;
return CUE_SUCCESS;
} else {
r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
ib_mc_address, IB_SIZE);
if (r)
return CUE_SCLEAN_FAILED;
r = amdgpu_cs_ctx_free(context_handle);
if (r)
return CUE_SCLEAN_FAILED;
r = amdgpu_device_deinitialize(device_handle);
if (r)
return CUE_SCLEAN_FAILED;
}
r = amdgpu_device_deinitialize(device_handle);
if (r)
return CUE_SCLEAN_FAILED;
return CUE_SUCCESS;
}
@ -240,26 +245,10 @@ static void free_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo)
memset(uvd_enc_bo, 0, sizeof(*uvd_enc_bo));
}
static bool uvd_enc_support(void)
{
int r;
struct drm_amdgpu_info_hw_ip info;
r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_UVD_ENC, 0, &info);
if (r)
return false;
else
return (info.available_rings?true:false);
}
static void amdgpu_cs_uvd_enc_create(void)
{
int len, r;
if (!uvd_enc_support())
return;
enc.width = 160;
enc.height = 128;
@ -296,9 +285,6 @@ static void amdgpu_cs_uvd_enc_session_init(void)
{
int len, r;
if (!uvd_enc_support())
return;
len = 0;
memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info));
len += sizeof(uve_session_info) / 4;
@ -354,8 +340,6 @@ static void amdgpu_cs_uvd_enc_encode(void)
vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5;
cpb_size = vbuf_size * 10;
if (!uvd_enc_support())
return;
num_resources = 0;
alloc_resource(&enc.fb, 4096, AMDGPU_GEM_DOMAIN_VRAM);
@ -489,9 +473,6 @@ static void amdgpu_cs_uvd_enc_destroy(void)
struct amdgpu_uvd_enc_bo sw_ctx;
int len, r;
if (!uvd_enc_support())
return;
num_resources = 0;
resources[num_resources++] = ib_handle;

61
tests/amdgpu/vce_tests.c
View File

@ -88,6 +88,27 @@ CU_TestInfo vce_tests[] = {
CU_TEST_INFO_NULL,
};
CU_BOOL suite_vce_tests_enable(void)
{
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
&minor_version, &device_handle))
return CU_FALSE;
family_id = device_handle->info.family_id;
if (amdgpu_device_deinitialize(device_handle))
return CU_FALSE;
if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) {
printf("\n\nThe ASIC NOT support VCE, suite disabled\n");
return CU_FALSE;
}
return CU_TRUE;
}
int suite_vce_tests_init(void)
{
int r;
@ -106,11 +127,6 @@ int suite_vce_tests_init(void)
family_id = device_handle->info.family_id;
vce_harvest_config = device_handle->info.vce_harvest_config;
if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) {
printf("\n\nThe ASIC NOT support VCE, all sub-tests will pass\n");
return CUE_SUCCESS;
}
r = amdgpu_cs_ctx_create(device_handle, &context_handle);
if (r)
return CUE_SINIT_FAILED;
@ -131,24 +147,18 @@ int suite_vce_tests_clean(void)
{
int r;
if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) {
r = amdgpu_device_deinitialize(device_handle);
if (r)
return CUE_SCLEAN_FAILED;
} else {
r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
ib_mc_address, IB_SIZE);
if (r)
return CUE_SCLEAN_FAILED;
r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
ib_mc_address, IB_SIZE);
if (r)
return CUE_SCLEAN_FAILED;
r = amdgpu_cs_ctx_free(context_handle);
if (r)
return CUE_SCLEAN_FAILED;
r = amdgpu_cs_ctx_free(context_handle);
if (r)
return CUE_SCLEAN_FAILED;
r = amdgpu_device_deinitialize(device_handle);
if (r)
return CUE_SCLEAN_FAILED;
}
r = amdgpu_device_deinitialize(device_handle);
if (r)
return CUE_SCLEAN_FAILED;
return CUE_SUCCESS;
}
@ -248,9 +258,6 @@ static void amdgpu_cs_vce_create(void)
unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
int len, r;
if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI)
return;
enc.width = vce_create[6];
enc.height = vce_create[7];
@ -444,9 +451,6 @@ static void amdgpu_cs_vce_encode(void)
unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
int i, r;
if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI)
return;
vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5;
cpb_size = vbuf_size * 10;
num_resources = 0;
@ -525,9 +529,6 @@ static void amdgpu_cs_vce_destroy(void)
{
int len, r;
if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI)
return;
num_resources = 0;
alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
resources[num_resources++] = enc.fb[0].handle;

72
tests/amdgpu/vcn_tests.c
View File

@ -82,6 +82,27 @@ CU_TestInfo vcn_tests[] = {
CU_TEST_INFO_NULL,
};
CU_BOOL suite_vcn_tests_enable(void)
{
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
&minor_version, &device_handle))
return CU_FALSE;
family_id = device_handle->info.family_id;
if (amdgpu_device_deinitialize(device_handle))
return CU_FALSE;
if (family_id < AMDGPU_FAMILY_RV) {
printf("\n\nThe ASIC NOT support VCN, suite disabled\n");
return CU_FALSE;
}
return CU_TRUE;
}
int suite_vcn_tests_init(void)
{
int r;
@ -93,11 +114,6 @@ int suite_vcn_tests_init(void)
family_id = device_handle->info.family_id;
if (family_id < AMDGPU_FAMILY_RV) {
printf("\n\nThe ASIC NOT support VCN, all sub-tests will pass\n");
return CUE_SUCCESS;
}
r = amdgpu_cs_ctx_create(device_handle, &context_handle);
if (r)
return CUE_SINIT_FAILED;
@ -116,26 +132,18 @@ int suite_vcn_tests_clean(void)
{
int r;
if (family_id < AMDGPU_FAMILY_RV) {
r = amdgpu_device_deinitialize(device_handle);
if (r)
return CUE_SCLEAN_FAILED;
} else {
r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
ib_mc_address, IB_SIZE);
if (r)
return CUE_SCLEAN_FAILED;
r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
ib_mc_address, IB_SIZE);
if (r)
return CUE_SCLEAN_FAILED;
r = amdgpu_cs_ctx_free(context_handle);
if (r)
return CUE_SCLEAN_FAILED;
r = amdgpu_cs_ctx_free(context_handle);
if (r)
return CUE_SCLEAN_FAILED;
r = amdgpu_device_deinitialize(device_handle);
if (r)
return CUE_SCLEAN_FAILED;
}
return CUE_SUCCESS;
r = amdgpu_device_deinitialize(device_handle);
if (r)
return CUE_SCLEAN_FAILED;
}
static int submit(unsigned ndw, unsigned ip)
@ -244,9 +252,6 @@ static void amdgpu_cs_vcn_dec_create(void)
struct amdgpu_vcn_bo msg_buf;
int len, r;
if (family_id < AMDGPU_FAMILY_RV)
return;
num_resources = 0;
alloc_resource(&msg_buf, 4096, AMDGPU_GEM_DOMAIN_GTT);
resources[num_resources++] = msg_buf.handle;
@ -282,9 +287,6 @@ static void amdgpu_cs_vcn_dec_decode(void)
int size, len, i, r;
uint8_t *dec;
if (family_id < AMDGPU_FAMILY_RV)
return;
size = 4*1024; /* msg */
size += 4*1024; /* fb */
size += 4096; /*it_scaling_table*/
@ -355,9 +357,6 @@ static void amdgpu_cs_vcn_dec_destroy(void)
struct amdgpu_vcn_bo msg_buf;
int len, r;
if (family_id < AMDGPU_FAMILY_RV)
return;
num_resources = 0;
alloc_resource(&msg_buf, 1024, AMDGPU_GEM_DOMAIN_GTT);
resources[num_resources++] = msg_buf.handle;
@ -387,24 +386,15 @@ static void amdgpu_cs_vcn_dec_destroy(void)
static void amdgpu_cs_vcn_enc_create(void)
{
if (family_id < AMDGPU_FAMILY_RV)
return;
/* TODO */
}
static void amdgpu_cs_vcn_enc_encode(void)
{
if (family_id < AMDGPU_FAMILY_RV)
return;
/* TODO */
}
static void amdgpu_cs_vcn_enc_destroy(void)
{
if (family_id < AMDGPU_FAMILY_RV)
return;
/* TODO */
}