Add drm_intel_bo_busy to query whether mapping a BO would block.
parent
19d6fadfa2
commit
8214a65ad1
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@ -220,6 +220,13 @@ int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
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return 0;
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}
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int drm_intel_bo_busy(drm_intel_bo *bo)
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{
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if (bo->bufmgr->bo_busy)
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return bo->bufmgr->bo_busy(bo);
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return 0;
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}
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int
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drm_intel_get_pipe_from_crtc_id (drm_intel_bufmgr *bufmgr, int crtc_id)
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{
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@ -107,6 +107,7 @@ int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t *tiling_mode,
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int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t *tiling_mode,
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uint32_t *swizzle_mode);
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int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t *name);
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int drm_intel_bo_busy(drm_intel_bo *bo);
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int drm_intel_bo_disable_reuse(drm_intel_bo *bo);
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@ -314,6 +314,22 @@ drm_intel_setup_reloc_list(drm_intel_bo *bo)
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return 0;
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}
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static int
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drm_intel_gem_bo_busy(drm_intel_bo *bo)
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{
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drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
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drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
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struct drm_i915_gem_busy busy;
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int ret;
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memset(&busy, 0, sizeof(busy));
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busy.handle = bo_gem->gem_handle;
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ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
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return (ret == 0 && busy.busy);
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}
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static drm_intel_bo *
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drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, const char *name,
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unsigned long size, unsigned int alignment,
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@ -344,8 +360,6 @@ drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, const char *name,
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pthread_mutex_lock(&bufmgr_gem->lock);
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/* Get a buffer out of the cache if available */
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if (bucket != NULL && bucket->num_entries > 0) {
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struct drm_i915_gem_busy busy;
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if (for_render) {
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/* Allocate new render-target BOs from the tail (MRU)
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* of the list, as it will likely be hot in the GPU cache
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@ -364,13 +378,8 @@ drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, const char *name,
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*/
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bo_gem = DRMLISTENTRY(drm_intel_bo_gem, bucket->head.next, head);
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memset(&busy, 0, sizeof(busy));
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busy.handle = bo_gem->gem_handle;
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ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
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alloc_from_cache = (ret == 0 && busy.busy == 0);
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if (alloc_from_cache) {
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if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
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alloc_from_cache = 1;
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DRMLISTDEL(&bo_gem->head);
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bucket->num_entries--;
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}
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@ -1491,6 +1500,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
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bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
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bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
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bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
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bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
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bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
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bufmgr_gem->bufmgr.debug = 0;
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bufmgr_gem->bufmgr.check_aperture_space = drm_intel_gem_check_aperture_space;
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@ -177,6 +177,12 @@ struct _drm_intel_bufmgr {
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*/
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int (*bo_flink)(drm_intel_bo *bo, uint32_t *name);
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/**
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* Returns 1 if mapping the buffer for write could cause the process
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* to block, due to the object being active in the GPU.
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*/
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int (*bo_busy)(drm_intel_bo *bo);
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int (*check_aperture_space)(drm_intel_bo **bo_array, int count);
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/**
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