tests/amdgpu: add dispatch test for gfx10
Signed-off-by: Flora Cui <flora.cui@amd.com>main
Flora Cui
parent
f2314a4871
commit
85393adb12
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@ -353,6 +353,12 @@ static const uint32_t bufferclear_cs_shader_gfx9[] = {
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0xbf810000
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};
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static const uint32_t bufferclear_cs_shader_gfx10[] = {
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0xD7460004, 0x04010C08, 0x7E000204, 0x7E020205,
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0x7E040206, 0x7E060207, 0xE01C2000, 0x80000004,
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0xBF810000
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};
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static const uint32_t bufferclear_cs_shader_registers_gfx9[][2] = {
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{0x2e12, 0x000C0041}, //{ mmCOMPUTE_PGM_RSRC1, 0x000C0041 },
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{0x2e13, 0x00000090}, //{ mmCOMPUTE_PGM_RSRC2, 0x00000090 },
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@ -369,6 +375,11 @@ static const uint32_t buffercopy_cs_shader_gfx9[] = {
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0xe01c2000, 0x80010200, 0xbf810000
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};
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static const uint32_t buffercopy_cs_shader_gfx10[] = {
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0xD7460001, 0x04010C08, 0xE00C2000, 0x80000201,
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0xBF8C3F70, 0xE01C2000, 0x80010201, 0xBF810000
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};
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static const uint32_t preamblecache_gfx9[] = {
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0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
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0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000,
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@ -657,6 +668,18 @@ struct amdgpu_test_shader memcpy_cs_hang_slow_rv = {
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1
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};
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unsigned int memcpy_cs_hang_slow_nv_codes[] = {
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0xd7460000, 0x04010c08, 0xe00c2000, 0x80000100,
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0xbf8c0f70, 0xe01ca000, 0x80010100, 0xbf810000
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};
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struct amdgpu_test_shader memcpy_cs_hang_slow_nv = {
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memcpy_cs_hang_slow_nv_codes,
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4,
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3,
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1
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};
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unsigned int memcpy_ps_hang_slow_ai_codes[] = {
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0xbefc000c, 0xbe8e017e, 0xbefe077e, 0xd4080000,
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0xd4090001, 0xd40c0100, 0xd40d0101, 0xf0800f00,
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@ -2446,6 +2469,9 @@ static int amdgpu_dispatch_load_cs_shader_hang_slow(uint32_t *ptr, int family)
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case AMDGPU_FAMILY_RV:
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shader = &memcpy_cs_hang_slow_rv;
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break;
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case AMDGPU_FAMILY_NV:
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shader = &memcpy_cs_hang_slow_nv;
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break;
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default:
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return -1;
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break;
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@ -2466,19 +2492,30 @@ static int amdgpu_dispatch_load_cs_shader_hang_slow(uint32_t *ptr, int family)
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}
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static int amdgpu_dispatch_load_cs_shader(uint8_t *ptr,
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int cs_type)
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int cs_type,
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uint32_t version)
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{
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uint32_t shader_size;
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const uint32_t *shader;
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switch (cs_type) {
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case CS_BUFFERCLEAR:
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shader = bufferclear_cs_shader_gfx9;
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shader_size = sizeof(bufferclear_cs_shader_gfx9);
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if (version == 9) {
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shader = bufferclear_cs_shader_gfx9;
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shader_size = sizeof(bufferclear_cs_shader_gfx9);
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} else if (version == 10) {
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shader = bufferclear_cs_shader_gfx10;
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shader_size = sizeof(bufferclear_cs_shader_gfx10);
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}
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break;
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case CS_BUFFERCOPY:
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shader = buffercopy_cs_shader_gfx9;
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shader_size = sizeof(buffercopy_cs_shader_gfx9);
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if (version == 9) {
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shader = buffercopy_cs_shader_gfx9;
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shader_size = sizeof(buffercopy_cs_shader_gfx9);
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} else if (version == 10) {
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shader = buffercopy_cs_shader_gfx10;
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shader_size = sizeof(buffercopy_cs_shader_gfx10);
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}
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break;
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case CS_HANG:
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shader = memcpy_ps_hang;
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@ -2493,7 +2530,7 @@ static int amdgpu_dispatch_load_cs_shader(uint8_t *ptr,
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return 0;
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}
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static int amdgpu_dispatch_init(uint32_t *ptr, uint32_t ip_type)
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static int amdgpu_dispatch_init(uint32_t *ptr, uint32_t ip_type, uint32_t version)
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{
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int i = 0;
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@ -2515,29 +2552,57 @@ static int amdgpu_dispatch_init(uint32_t *ptr, uint32_t ip_type)
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ptr[i++] = 0x218;
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ptr[i++] = 0;
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/* Set new sh registers in GFX10 to 0 */
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if (version == 10) {
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/* mmCOMPUTE_SHADER_CHKSUM */
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ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
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ptr[i++] = 0x22a;
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ptr[i++] = 0;
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/* mmCOMPUTE_REQ_CTRL */
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ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 6);
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ptr[i++] = 0x222;
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i += 6;
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/* mmCP_COHER_START_DELAY */
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ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
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ptr[i++] = 0x7b;
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ptr[i++] = 0x20;
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}
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return i;
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}
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static int amdgpu_dispatch_write_cumask(uint32_t *ptr)
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static int amdgpu_dispatch_write_cumask(uint32_t *ptr, uint32_t version)
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{
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int i = 0;
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/* Issue commands to set cu mask used in current dispatch */
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/* set mmCOMPUTE_STATIC_THREAD_MGMT_SE1 - mmCOMPUTE_STATIC_THREAD_MGMT_SE0 */
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ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2);
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ptr[i++] = 0x216;
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ptr[i++] = 0xffffffff;
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ptr[i++] = 0xffffffff;
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/* set mmCOMPUTE_STATIC_THREAD_MGMT_SE3 - mmCOMPUTE_STATIC_THREAD_MGMT_SE2 */
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ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2);
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ptr[i++] = 0x219;
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ptr[i++] = 0xffffffff;
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ptr[i++] = 0xffffffff;
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if (version == 9) {
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/* set mmCOMPUTE_STATIC_THREAD_MGMT_SE1 - mmCOMPUTE_STATIC_THREAD_MGMT_SE0 */
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ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2);
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ptr[i++] = 0x216;
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ptr[i++] = 0xffffffff;
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ptr[i++] = 0xffffffff;
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/* set mmCOMPUTE_STATIC_THREAD_MGMT_SE3 - mmCOMPUTE_STATIC_THREAD_MGMT_SE2 */
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ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2);
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ptr[i++] = 0x219;
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ptr[i++] = 0xffffffff;
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ptr[i++] = 0xffffffff;
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} else if (version == 10) {
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/* set mmCOMPUTE_STATIC_THREAD_MGMT_SE1 - mmCOMPUTE_STATIC_THREAD_MGMT_SE0 */
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ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG_INDEX, 2);
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ptr[i++] = 0x30000216;
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ptr[i++] = 0xffffffff;
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ptr[i++] = 0xffffffff;
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/* set mmCOMPUTE_STATIC_THREAD_MGMT_SE3 - mmCOMPUTE_STATIC_THREAD_MGMT_SE2 */
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ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG_INDEX, 2);
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ptr[i++] = 0x30000219;
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ptr[i++] = 0xffffffff;
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ptr[i++] = 0xffffffff;
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}
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return i;
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}
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static int amdgpu_dispatch_write2hw(uint32_t *ptr, uint64_t shader_addr)
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static int amdgpu_dispatch_write2hw(uint32_t *ptr, uint64_t shader_addr, uint32_t version)
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{
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int i, j;
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@ -2557,12 +2622,20 @@ static int amdgpu_dispatch_write2hw(uint32_t *ptr, uint64_t shader_addr)
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ptr[i++] = bufferclear_cs_shader_registers_gfx9[j][1];
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}
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if (version == 10) {
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/* mmCOMPUTE_PGM_RSRC3 */
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ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
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ptr[i++] = 0x228;
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ptr[i++] = 0;
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}
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return i;
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}
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static void amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
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uint32_t ip_type,
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uint32_t ring)
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uint32_t ring,
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uint32_t version)
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{
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amdgpu_context_handle context_handle;
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amdgpu_bo_handle bo_dst, bo_shader, bo_cmd, resources[3];
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@ -2598,7 +2671,7 @@ static void amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
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CU_ASSERT_EQUAL(r, 0);
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memset(ptr_shader, 0, bo_shader_size);
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r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCLEAR);
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r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCLEAR, version);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
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@ -2608,13 +2681,13 @@ static void amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
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CU_ASSERT_EQUAL(r, 0);
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i = 0;
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i += amdgpu_dispatch_init(ptr_cmd + i, ip_type);
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i += amdgpu_dispatch_init(ptr_cmd + i, ip_type, version);
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/* Issue commands to set cu mask used in current dispatch */
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i += amdgpu_dispatch_write_cumask(ptr_cmd + i);
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i += amdgpu_dispatch_write_cumask(ptr_cmd + i, version);
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/* Writes shader state to HW */
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i += amdgpu_dispatch_write2hw(ptr_cmd + i, mc_address_shader);
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i += amdgpu_dispatch_write2hw(ptr_cmd + i, mc_address_shader, version);
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/* Write constant data */
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/* Writes the UAV constant data to the SGPRs. */
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@ -2623,7 +2696,10 @@ static void amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
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ptr_cmd[i++] = mc_address_dst;
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ptr_cmd[i++] = (mc_address_dst >> 32) | 0x100000;
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ptr_cmd[i++] = 0x400;
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ptr_cmd[i++] = 0x74fac;
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if (version == 9)
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ptr_cmd[i++] = 0x74fac;
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else if (version == 10)
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ptr_cmd[i++] = 0x1104bfac;
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/* Sets a range of pixel shader constants */
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ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
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@ -2705,6 +2781,7 @@ static void amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
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static void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
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uint32_t ip_type,
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uint32_t ring,
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uint32_t version,
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int hang)
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{
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amdgpu_context_handle context_handle;
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@ -2744,7 +2821,7 @@ static void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
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memset(ptr_shader, 0, bo_shader_size);
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cs_type = hang ? CS_HANG : CS_BUFFERCOPY;
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r = amdgpu_dispatch_load_cs_shader(ptr_shader, cs_type);
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r = amdgpu_dispatch_load_cs_shader(ptr_shader, cs_type, version);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
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@ -2762,13 +2839,13 @@ static void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
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memset(ptr_src, 0x55, bo_dst_size);
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i = 0;
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i += amdgpu_dispatch_init(ptr_cmd + i, ip_type);
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i += amdgpu_dispatch_init(ptr_cmd + i, ip_type, version);
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/* Issue commands to set cu mask used in current dispatch */
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i += amdgpu_dispatch_write_cumask(ptr_cmd + i);
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i += amdgpu_dispatch_write_cumask(ptr_cmd + i, version);
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/* Writes shader state to HW */
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i += amdgpu_dispatch_write2hw(ptr_cmd + i, mc_address_shader);
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i += amdgpu_dispatch_write2hw(ptr_cmd + i, mc_address_shader, version);
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/* Write constant data */
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/* Writes the texture resource constants data to the SGPRs */
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@ -2777,7 +2854,10 @@ static void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
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ptr_cmd[i++] = mc_address_src;
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ptr_cmd[i++] = (mc_address_src >> 32) | 0x100000;
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ptr_cmd[i++] = 0x400;
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ptr_cmd[i++] = 0x74fac;
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if (version == 9)
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ptr_cmd[i++] = 0x74fac;
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else if (version == 10)
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ptr_cmd[i++] = 0x1104bfac;
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/* Writes the UAV constant data to the SGPRs. */
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ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
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@ -2785,7 +2865,10 @@ static void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
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ptr_cmd[i++] = mc_address_dst;
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ptr_cmd[i++] = (mc_address_dst >> 32) | 0x100000;
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ptr_cmd[i++] = 0x400;
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ptr_cmd[i++] = 0x74fac;
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if (version == 9)
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ptr_cmd[i++] = 0x74fac;
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else if (version == 10)
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ptr_cmd[i++] = 0x1104bfac;
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/* clear mmCOMPUTE_RESOURCE_LIMITS */
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ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
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@ -2869,16 +2952,22 @@ static void amdgpu_compute_dispatch_test(void)
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{
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int r;
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struct drm_amdgpu_info_hw_ip info;
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uint32_t ring_id;
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uint32_t ring_id, version;
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r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_COMPUTE, 0, &info);
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CU_ASSERT_EQUAL(r, 0);
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if (!info.available_rings)
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printf("SKIP ... as there's no compute ring\n");
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version = info.hw_ip_version_major;
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if (version != 9 && version != 10) {
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printf("SKIP ... unsupported gfx version %d\n", version);
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return;
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}
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for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
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amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_COMPUTE, ring_id);
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amdgpu_memcpy_dispatch_test(device_handle, AMDGPU_HW_IP_COMPUTE, ring_id, 0);
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amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_COMPUTE, ring_id, version);
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amdgpu_memcpy_dispatch_test(device_handle, AMDGPU_HW_IP_COMPUTE, ring_id, version, 0);
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}
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}
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@ -2886,16 +2975,22 @@ static void amdgpu_gfx_dispatch_test(void)
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{
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int r;
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struct drm_amdgpu_info_hw_ip info;
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uint32_t ring_id;
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uint32_t ring_id, version;
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r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
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CU_ASSERT_EQUAL(r, 0);
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if (!info.available_rings)
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printf("SKIP ... as there's no graphics ring\n");
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version = info.hw_ip_version_major;
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if (version != 9 && version != 10) {
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printf("SKIP ... unsupported gfx version %d\n", version);
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return;
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}
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for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
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amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_GFX, ring_id);
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amdgpu_memcpy_dispatch_test(device_handle, AMDGPU_HW_IP_GFX, ring_id, 0);
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amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_GFX, ring_id, version);
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amdgpu_memcpy_dispatch_test(device_handle, AMDGPU_HW_IP_GFX, ring_id, version, 0);
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}
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}
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@ -2903,22 +2998,28 @@ void amdgpu_dispatch_hang_helper(amdgpu_device_handle device_handle, uint32_t ip
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{
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int r;
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struct drm_amdgpu_info_hw_ip info;
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uint32_t ring_id;
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uint32_t ring_id, version;
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r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &info);
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CU_ASSERT_EQUAL(r, 0);
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if (!info.available_rings)
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printf("SKIP ... as there's no ring for ip %d\n", ip_type);
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version = info.hw_ip_version_major;
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if (version != 9 && version != 10) {
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printf("SKIP ... unsupported gfx version %d\n", version);
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return;
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}
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for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
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amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, 0);
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amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, 1);
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amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, 0);
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amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, version, 0);
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amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, version, 1);
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amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, version, 0);
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}
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}
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static void amdgpu_memcpy_dispatch_hang_slow_test(amdgpu_device_handle device_handle,
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uint32_t ip_type, uint32_t ring)
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uint32_t ip_type, uint32_t ring, int version)
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{
|
||||
amdgpu_context_handle context_handle;
|
||||
amdgpu_bo_handle bo_src, bo_dst, bo_shader, bo_cmd, resources[4];
|
||||
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|
@ -2977,13 +3078,13 @@ static void amdgpu_memcpy_dispatch_hang_slow_test(amdgpu_device_handle device_ha
|
|||
memset(ptr_src, 0x55, bo_dst_size);
|
||||
|
||||
i = 0;
|
||||
i += amdgpu_dispatch_init(ptr_cmd + i, ip_type);
|
||||
i += amdgpu_dispatch_init(ptr_cmd + i, ip_type, version);
|
||||
|
||||
/* Issue commands to set cu mask used in current dispatch */
|
||||
i += amdgpu_dispatch_write_cumask(ptr_cmd + i);
|
||||
i += amdgpu_dispatch_write_cumask(ptr_cmd + i, version);
|
||||
|
||||
/* Writes shader state to HW */
|
||||
i += amdgpu_dispatch_write2hw(ptr_cmd + i, mc_address_shader);
|
||||
i += amdgpu_dispatch_write2hw(ptr_cmd + i, mc_address_shader, version);
|
||||
|
||||
/* Write constant data */
|
||||
/* Writes the texture resource constants data to the SGPRs */
|
||||
|
|
@ -2992,7 +3093,10 @@ static void amdgpu_memcpy_dispatch_hang_slow_test(amdgpu_device_handle device_ha
|
|||
ptr_cmd[i++] = mc_address_src;
|
||||
ptr_cmd[i++] = (mc_address_src >> 32) | 0x100000;
|
||||
ptr_cmd[i++] = 0x400000;
|
||||
ptr_cmd[i++] = 0x74fac;
|
||||
if (version == 9)
|
||||
ptr_cmd[i++] = 0x74fac;
|
||||
else if (version == 10)
|
||||
ptr_cmd[i++] = 0x1104bfac;
|
||||
|
||||
/* Writes the UAV constant data to the SGPRs. */
|
||||
ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
|
||||
|
|
@ -3000,7 +3104,10 @@ static void amdgpu_memcpy_dispatch_hang_slow_test(amdgpu_device_handle device_ha
|
|||
ptr_cmd[i++] = mc_address_dst;
|
||||
ptr_cmd[i++] = (mc_address_dst >> 32) | 0x100000;
|
||||
ptr_cmd[i++] = 0x400000;
|
||||
ptr_cmd[i++] = 0x74fac;
|
||||
if (version == 9)
|
||||
ptr_cmd[i++] = 0x74fac;
|
||||
else if (version == 10)
|
||||
ptr_cmd[i++] = 0x1104bfac;
|
||||
|
||||
/* clear mmCOMPUTE_RESOURCE_LIMITS */
|
||||
ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
|
||||
|
|
@ -3072,17 +3179,23 @@ void amdgpu_dispatch_hang_slow_helper(amdgpu_device_handle device_handle, uint32
|
|||
{
|
||||
int r;
|
||||
struct drm_amdgpu_info_hw_ip info;
|
||||
uint32_t ring_id;
|
||||
uint32_t ring_id, version;
|
||||
|
||||
r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &info);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
if (!info.available_rings)
|
||||
printf("SKIP ... as there's no ring for ip %d\n", ip_type);
|
||||
|
||||
version = info.hw_ip_version_major;
|
||||
if (version != 9 && version != 10) {
|
||||
printf("SKIP ... unsupported gfx version %d\n", version);
|
||||
return;
|
||||
}
|
||||
|
||||
for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
|
||||
amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, 0);
|
||||
amdgpu_memcpy_dispatch_hang_slow_test(device_handle, ip_type, ring_id);
|
||||
amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, 0);
|
||||
amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, version, 0);
|
||||
amdgpu_memcpy_dispatch_hang_slow_test(device_handle, ip_type, ring_id, version);
|
||||
amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, version, 0);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue