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Clean up xgi_(en|dis)able_(mmio|ge) and move to xgi_misc.c.

main
Ian Romanick 2007-08-14 13:18:44 -07:00
parent 15f841bd52
commit 891714d8d7
3 changed files with 171 additions and 110 deletions
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5
linux-core/xgi_drv.h
View File

@ -87,6 +87,11 @@ extern void xgi_pcie_lut_cleanup(struct xgi_info * info);
extern void *xgi_find_pcie_virt(struct xgi_info * info, u32 address); extern void *xgi_find_pcie_virt(struct xgi_info * info, u32 address);
extern void xgi_enable_mmio(struct xgi_info * info);
extern void xgi_disable_mmio(struct xgi_info * info);
extern void xgi_enable_ge(struct xgi_info * info);
extern void xgi_disable_ge(struct xgi_info * info);
extern int xgi_alloc_ioctl(struct drm_device * dev, void * data, extern int xgi_alloc_ioctl(struct drm_device * dev, void * data,
struct drm_file * filp); struct drm_file * filp);
extern int xgi_free_ioctl(struct drm_device * dev, void * data, extern int xgi_free_ioctl(struct drm_device * dev, void * data,

126
linux-core/xgi_misc.c
View File

@ -374,3 +374,129 @@ void xgi_waitfor_pci_idle(struct xgi_info * info)
} }
} }
} }
void xgi_enable_mmio(struct xgi_info * info)
{
u8 protect = 0;
u8 temp;
/* Unprotect registers */
DRM_WRITE8(info->mmio_map, 0x3C4, 0x11);
protect = DRM_READ8(info->mmio_map, 0x3C5);
DRM_WRITE8(info->mmio_map, 0x3C5, 0x92);
DRM_WRITE8(info->mmio_map, 0x3D4, 0x3A);
temp = DRM_READ8(info->mmio_map, 0x3D5);
DRM_WRITE8(info->mmio_map, 0x3D5, temp | 0x20);
/* Enable MMIO */
DRM_WRITE8(info->mmio_map, 0x3D4, 0x39);
temp = DRM_READ8(info->mmio_map, 0x3D5);
DRM_WRITE8(info->mmio_map, 0x3D5, temp | 0x01);
/* Protect registers */
OUT3C5B(info->mmio_map, 0x11, protect);
}
void xgi_disable_mmio(struct xgi_info * info)
{
u8 protect = 0;
u8 temp;
/* Unprotect registers */
DRM_WRITE8(info->mmio_map, 0x3C4, 0x11);
protect = DRM_READ8(info->mmio_map, 0x3C5);
DRM_WRITE8(info->mmio_map, 0x3C5, 0x92);
/* Disable MMIO access */
DRM_WRITE8(info->mmio_map, 0x3D4, 0x39);
temp = DRM_READ8(info->mmio_map, 0x3D5);
DRM_WRITE8(info->mmio_map, 0x3D5, temp & 0xFE);
/* Protect registers */
OUT3C5B(info->mmio_map, 0x11, protect);
}
void xgi_enable_ge(struct xgi_info * info)
{
u8 bOld3cf2a;
int wait = 0;
OUT3C5B(info->mmio_map, 0x11, 0x92);
/* Save and close dynamic gating
*/
bOld3cf2a = IN3CFB(info->mmio_map, XGI_MISC_CTRL);
OUT3CFB(info->mmio_map, XGI_MISC_CTRL, bOld3cf2a & ~EN_GEPWM);
/* Enable 2D and 3D GE
*/
OUT3X5B(info->mmio_map, XGI_GE_CNTL, (GE_ENABLE | GE_ENABLE_3D));
wait = 10;
while (wait--) {
DRM_READ8(info->mmio_map, 0x36);
}
/* Reset both 3D and 2D engine
*/
OUT3X5B(info->mmio_map, XGI_GE_CNTL,
(GE_ENABLE | GE_RESET | GE_ENABLE_3D));
wait = 10;
while (wait--) {
DRM_READ8(info->mmio_map, 0x36);
}
OUT3X5B(info->mmio_map, XGI_GE_CNTL, (GE_ENABLE | GE_ENABLE_3D));
wait = 10;
while (wait--) {
DRM_READ8(info->mmio_map, 0x36);
}
/* Enable 2D engine only
*/
OUT3X5B(info->mmio_map, XGI_GE_CNTL, GE_ENABLE);
/* Enable 2D+3D engine
*/
OUT3X5B(info->mmio_map, XGI_GE_CNTL, (GE_ENABLE | GE_ENABLE_3D));
/* Restore dynamic gating
*/
OUT3CFB(info->mmio_map, XGI_MISC_CTRL, bOld3cf2a);
}
void xgi_disable_ge(struct xgi_info * info)
{
int wait = 0;
OUT3X5B(info->mmio_map, XGI_GE_CNTL, (GE_ENABLE | GE_ENABLE_3D));
wait = 10;
while (wait--) {
DRM_READ8(info->mmio_map, 0x36);
}
/* Reset both 3D and 2D engine
*/
OUT3X5B(info->mmio_map, XGI_GE_CNTL,
(GE_ENABLE | GE_RESET | GE_ENABLE_3D));
wait = 10;
while (wait--) {
DRM_READ8(info->mmio_map, 0x36);
}
OUT3X5B(info->mmio_map, XGI_GE_CNTL, (GE_ENABLE | GE_ENABLE_3D));
wait = 10;
while (wait--) {
DRM_READ8(info->mmio_map, 0x36);
}
/* Disable 2D engine and 3D engine.
*/
OUT3X5B(info->mmio_map, XGI_GE_CNTL, 0);
}

150
linux-core/xgi_regs.h
View File

@ -30,8 +30,6 @@
#include "drmP.h" #include "drmP.h"
#include "drm.h" #include "drm.h"
#define BASE_3D_ENG 0x2800
#define MAKE_MASK(bits) ((1U << (bits)) - 1) #define MAKE_MASK(bits) ((1U << (bits)) - 1)
#define ONE_BIT_MASK MAKE_MASK(1) #define ONE_BIT_MASK MAKE_MASK(1)
@ -39,6 +37,46 @@
#define TWENTYONE_BIT_MASK MAKE_MASK(21) #define TWENTYONE_BIT_MASK MAKE_MASK(21)
#define TWENTYTWO_BIT_MASK MAKE_MASK(22) #define TWENTYTWO_BIT_MASK MAKE_MASK(22)
/* Port 0x3d4/0x3d5, index 0x2a */
#define XGI_INTERFACE_SEL 0x2a
#define DUAL_64BIT (1U<<7)
#define INTERNAL_32BIT (1U<<6)
#define EN_SEP_WR (1U<<5)
#define POWER_DOWN_SEL (1U<<4)
/*#define RESERVED_3 (1U<<3) */
#define SUBS_MCLK_PCICLK (1U<<2)
#define MEM_SIZE_MASK (3<<0)
#define MEM_SIZE_32MB (0<<0)
#define MEM_SIZE_64MB (1<<0)
#define MEM_SIZE_128MB (2<<0)
#define MEM_SIZE_256MB (3<<0)
/* Port 0x3d4/0x3d5, index 0x36 */
#define XGI_GE_CNTL 0x36
#define GE_ENABLE (1U<<7)
/*#define RESERVED_6 (1U<<6) */
/*#define RESERVED_5 (1U<<5) */
#define GE_RESET (1U<<4)
/*#define RESERVED_3 (1U<<3) */
#define GE_ENABLE_3D (1U<<2)
/*#define RESERVED_1 (1U<<1) */
/*#define RESERVED_0 (1U<<0) */
/* Port 0x3ce/0x3cf, index 0x2a */
#define XGI_MISC_CTRL 0x2a
#define MOTION_VID_SUSPEND (1U<<7)
#define DVI_CRTC_TIMING_SEL (1U<<6)
#define LCD_SEL_CTL_NEW (1U<<5)
#define LCD_SEL_EXT_DELYCTRL (1U<<4)
#define REG_LCDDPARST (1U<<3)
#define LCD2DPAOFF (1U<<2)
/*#define RESERVED_1 (1U<<1) */
#define EN_GEPWM (1U<<0) /* Enable GE power management */
#define BASE_3D_ENG 0x2800
#define M2REG_FLUSH_ENGINE_ADDRESS 0x000 #define M2REG_FLUSH_ENGINE_ADDRESS 0x000
#define M2REG_FLUSH_ENGINE_COMMAND 0x00 #define M2REG_FLUSH_ENGINE_COMMAND 0x00
#define M2REG_FLUSH_FLIP_ENGINE_MASK (ONE_BIT_MASK<<21) #define M2REG_FLUSH_FLIP_ENGINE_MASK (ONE_BIT_MASK<<21)
@ -133,114 +171,6 @@ static inline void dwWriteReg(struct drm_map * map, u32 addr, u32 data)
} }
static inline void xgi_enable_mmio(struct xgi_info * info)
{
u8 protect = 0;
u8 temp;
/* Unprotect registers */
DRM_WRITE8(info->mmio_map, 0x3C4, 0x11);
protect = DRM_READ8(info->mmio_map, 0x3C5);
DRM_WRITE8(info->mmio_map, 0x3C5, 0x92);
DRM_WRITE8(info->mmio_map, 0x3D4, 0x3A);
temp = DRM_READ8(info->mmio_map, 0x3D5);
DRM_WRITE8(info->mmio_map, 0x3D5, temp | 0x20);
/* Enable MMIO */
DRM_WRITE8(info->mmio_map, 0x3D4, 0x39);
temp = DRM_READ8(info->mmio_map, 0x3D5);
DRM_WRITE8(info->mmio_map, 0x3D5, temp | 0x01);
/* Protect registers */
OUT3C5B(info->mmio_map, 0x11, protect);
}
static inline void xgi_disable_mmio(struct xgi_info * info)
{
u8 protect = 0;
u8 temp;
/* Unprotect registers */
DRM_WRITE8(info->mmio_map, 0x3C4, 0x11);
protect = DRM_READ8(info->mmio_map, 0x3C5);
DRM_WRITE8(info->mmio_map, 0x3C5, 0x92);
/* Disable MMIO access */
DRM_WRITE8(info->mmio_map, 0x3D4, 0x39);
temp = DRM_READ8(info->mmio_map, 0x3D5);
DRM_WRITE8(info->mmio_map, 0x3D5, temp & 0xFE);
/* Protect registers */
OUT3C5B(info->mmio_map, 0x11, protect);
}
static inline void xgi_enable_ge(struct xgi_info * info)
{
unsigned char bOld3cf2a = 0;
int wait = 0;
// Enable GE
OUT3C5B(info->mmio_map, 0x11, 0x92);
// Save and close dynamic gating
bOld3cf2a = IN3CFB(info->mmio_map, 0x2a);
OUT3CFB(info->mmio_map, 0x2a, bOld3cf2a & 0xfe);
// Reset both 3D and 2D engine
OUT3X5B(info->mmio_map, 0x36, 0x84);
wait = 10;
while (wait--) {
DRM_READ8(info->mmio_map, 0x36);
}
OUT3X5B(info->mmio_map, 0x36, 0x94);
wait = 10;
while (wait--) {
DRM_READ8(info->mmio_map, 0x36);
}
OUT3X5B(info->mmio_map, 0x36, 0x84);
wait = 10;
while (wait--) {
DRM_READ8(info->mmio_map, 0x36);
}
// Enable 2D engine only
OUT3X5B(info->mmio_map, 0x36, 0x80);
// Enable 2D+3D engine
OUT3X5B(info->mmio_map, 0x36, 0x84);
// Restore dynamic gating
OUT3CFB(info->mmio_map, 0x2a, bOld3cf2a);
}
static inline void xgi_disable_ge(struct xgi_info * info)
{
int wait = 0;
// Reset both 3D and 2D engine
OUT3X5B(info->mmio_map, 0x36, 0x84);
wait = 10;
while (wait--) {
DRM_READ8(info->mmio_map, 0x36);
}
OUT3X5B(info->mmio_map, 0x36, 0x94);
wait = 10;
while (wait--) {
DRM_READ8(info->mmio_map, 0x36);
}
OUT3X5B(info->mmio_map, 0x36, 0x84);
wait = 10;
while (wait--) {
DRM_READ8(info->mmio_map, 0x36);
}
// Disable 2D engine only
OUT3X5B(info->mmio_map, 0x36, 0);
}
static inline void xgi_enable_dvi_interrupt(struct xgi_info * info) static inline void xgi_enable_dvi_interrupt(struct xgi_info * info)
{ {
OUT3CFB(info->mmio_map, 0x39, IN3CFB(info->mmio_map, 0x39) & ~0x01); //Set 3cf.39 bit 0 to 0 OUT3CFB(info->mmio_map, 0x39, IN3CFB(info->mmio_map, 0x39) & ~0x01); //Set 3cf.39 bit 0 to 0