intel: Add support for softpin
Softpin allows userspace to take greater control of GPU virtual address space and eliminates the need of relocations. It can also be used to mirror addresses between GPU and CPU (shared virtual memory). Calls to drm_intel_bo_emit_reloc are still required to build the list of drm_i915_gem_exec_objects at exec time, but no entries in relocs are created. Self-relocs don't make any sense for softpinned objects and can indicate a programming errors, thus are forbidden. Softpinned objects are marked by asterisk in debug dumps. Cc: Thomas Daniel <thomas.daniel@intel.com> Cc: Kristian Høgsberg <krh@bitplanet.net> Cc: Zou Nanhai <nanhai.zou@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>main
Michał Winiarski
Kristian Høgsberg Kristensen
parent
5453f89b70
commit
8b4d57e7b7
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@ -260,6 +260,15 @@ drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
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return 0;
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}
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int
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drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset)
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{
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if (bo->bufmgr->bo_set_softpin_offset)
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return bo->bufmgr->bo_set_softpin_offset(bo, offset);
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return -ENODEV;
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}
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int
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drm_intel_bo_disable_reuse(drm_intel_bo *bo)
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{
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@ -165,6 +165,7 @@ int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name);
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int drm_intel_bo_busy(drm_intel_bo *bo);
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int drm_intel_bo_madvise(drm_intel_bo *bo, int madv);
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int drm_intel_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable);
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int drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset);
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int drm_intel_bo_disable_reuse(drm_intel_bo *bo);
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int drm_intel_bo_is_reusable(drm_intel_bo *bo);
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@ -200,6 +200,13 @@ struct _drm_intel_bo_gem {
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drm_intel_reloc_target *reloc_target_info;
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/** Number of entries in relocs */
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int reloc_count;
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/** Array of BOs that are referenced by this buffer and will be softpinned */
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drm_intel_bo **softpin_target;
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/** Number softpinned BOs that are referenced by this buffer */
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int softpin_target_count;
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/** Maximum amount of softpinned BOs that are referenced by this buffer */
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int softpin_target_size;
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/** Mapped address for the buffer, saved across map/unmap cycles */
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void *mem_virtual;
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/** GTT virtual address for the buffer, saved across map/unmap cycles */
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@ -261,6 +268,11 @@ struct _drm_intel_bo_gem {
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*/
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bool use_48b_address_range;
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/**
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* Whether this buffer is softpinned at offset specified by the user
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*/
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bool is_softpin;
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/**
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* Size in bytes of this buffer and its relocation descendents.
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*
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@ -414,8 +426,9 @@ drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
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drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
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drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
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if (bo_gem->relocs == NULL) {
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DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
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if (bo_gem->relocs == NULL && bo_gem->softpin_target == NULL) {
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DBG("%2d: %d %s(%s)\n", i, bo_gem->gem_handle,
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bo_gem->is_softpin ? "*" : "",
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bo_gem->name);
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continue;
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}
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@ -425,18 +438,33 @@ drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
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drm_intel_bo_gem *target_gem =
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(drm_intel_bo_gem *) target_bo;
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DBG("%2d: %d (%s)@0x%08x %08x -> "
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"%d (%s)@0x%08x %08x + 0x%08x\n",
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DBG("%2d: %d %s(%s)@0x%016llx -> "
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"%d (%s)@0x%016llx + 0x%08x\n",
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i,
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bo_gem->gem_handle, bo_gem->name,
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upper_32_bits(bo_gem->relocs[j].offset),
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lower_32_bits(bo_gem->relocs[j].offset),
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bo_gem->gem_handle,
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bo_gem->is_softpin ? "*" : "",
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bo_gem->name,
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(unsigned long long) bo_gem->relocs[j].offset,
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target_gem->gem_handle,
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target_gem->name,
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upper_32_bits(target_bo->offset64),
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lower_32_bits(target_bo->offset64),
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(unsigned long long) target_bo->offset64,
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bo_gem->relocs[j].delta);
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}
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for (j = 0; j < bo_gem->softpin_target_count; j++) {
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drm_intel_bo *target_bo = bo_gem->softpin_target[j];
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drm_intel_bo_gem *target_gem =
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(drm_intel_bo_gem *) target_bo;
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DBG("%2d: %d %s(%s) -> "
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"%d *(%s)@0x%016lx\n",
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i,
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bo_gem->gem_handle,
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bo_gem->is_softpin ? "*" : "",
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bo_gem->name,
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target_gem->gem_handle,
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target_gem->name,
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target_bo->offset64);
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}
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}
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}
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@ -506,6 +534,8 @@ drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
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flags |= EXEC_OBJECT_NEEDS_FENCE;
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if (bo_gem->use_48b_address_range)
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flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
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if (bo_gem->is_softpin)
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flags |= EXEC_OBJECT_PINNED;
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if (bo_gem->validate_index != -1) {
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bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |= flags;
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@ -535,7 +565,8 @@ drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
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bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
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bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
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bufmgr_gem->exec2_objects[index].alignment = bo->align;
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bufmgr_gem->exec2_objects[index].offset = 0;
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bufmgr_gem->exec2_objects[index].offset = bo_gem->is_softpin ?
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bo->offset64 : 0;
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bufmgr_gem->exec_bos[index] = bo;
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bufmgr_gem->exec2_objects[index].flags = flags;
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bufmgr_gem->exec2_objects[index].rsvd1 = 0;
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@ -1291,8 +1322,12 @@ drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
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time);
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}
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}
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for (i = 0; i < bo_gem->softpin_target_count; i++)
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drm_intel_gem_bo_unreference_locked_timed(bo_gem->softpin_target[i],
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time);
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bo_gem->reloc_count = 0;
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bo_gem->used_as_reloc_target = false;
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bo_gem->softpin_target_count = 0;
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DBG("bo_unreference final: %d (%s)\n",
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bo_gem->gem_handle, bo_gem->name);
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@ -1306,6 +1341,11 @@ drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
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free(bo_gem->relocs);
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bo_gem->relocs = NULL;
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}
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if (bo_gem->softpin_target) {
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free(bo_gem->softpin_target);
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bo_gem->softpin_target = NULL;
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bo_gem->softpin_target_size = 0;
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}
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/* Clear any left-over mappings */
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if (bo_gem->map_count) {
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@ -1943,14 +1983,6 @@ do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
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bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
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}
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bo_gem->relocs[bo_gem->reloc_count].offset = offset;
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bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
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bo_gem->relocs[bo_gem->reloc_count].target_handle =
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target_bo_gem->gem_handle;
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bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
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bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
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bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset64;
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bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
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if (target_bo != bo)
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drm_intel_gem_bo_reference(target_bo);
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@ -1960,6 +1992,13 @@ do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
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else
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bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
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bo_gem->relocs[bo_gem->reloc_count].offset = offset;
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bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
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bo_gem->relocs[bo_gem->reloc_count].target_handle =
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target_bo_gem->gem_handle;
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bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
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bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
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bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset64;
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bo_gem->reloc_count++;
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return 0;
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@ -1972,13 +2011,55 @@ drm_intel_gem_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable)
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bo_gem->use_48b_address_range = enable;
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}
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static int
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drm_intel_gem_bo_add_softpin_target(drm_intel_bo *bo, drm_intel_bo *target_bo)
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{
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drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
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drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
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drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
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if (bo_gem->has_error)
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return -ENOMEM;
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if (target_bo_gem->has_error) {
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bo_gem->has_error = true;
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return -ENOMEM;
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}
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if (!target_bo_gem->is_softpin)
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return -EINVAL;
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if (target_bo_gem == bo_gem)
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return -EINVAL;
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if (bo_gem->softpin_target_count == bo_gem->softpin_target_size) {
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int new_size = bo_gem->softpin_target_size * 2;
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if (new_size == 0)
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new_size = bufmgr_gem->max_relocs;
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bo_gem->softpin_target = realloc(bo_gem->softpin_target, new_size *
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sizeof(drm_intel_bo *));
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if (!bo_gem->softpin_target)
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return -ENOMEM;
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bo_gem->softpin_target_size = new_size;
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}
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bo_gem->softpin_target[bo_gem->softpin_target_count] = target_bo;
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drm_intel_gem_bo_reference(target_bo);
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bo_gem->softpin_target_count++;
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return 0;
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}
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static int
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drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
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drm_intel_bo *target_bo, uint32_t target_offset,
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uint32_t read_domains, uint32_t write_domain)
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{
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drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
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drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *)target_bo;
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if (target_bo_gem->is_softpin)
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return drm_intel_gem_bo_add_softpin_target(bo, target_bo);
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else
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return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
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read_domains, write_domain,
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!bufmgr_gem->fenced_relocs);
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@ -2014,6 +2095,8 @@ drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
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*
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* Any further drm_intel_bufmgr_check_aperture_space() queries
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* involving this buffer in the tree are undefined after this call.
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*
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* This also removes all softpinned targets being referenced by the BO.
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*/
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void
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drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
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@ -2040,6 +2123,12 @@ drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
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}
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bo_gem->reloc_count = start;
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for (i = 0; i < bo_gem->softpin_target_count; i++) {
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drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) bo_gem->softpin_target[i];
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drm_intel_gem_bo_unreference_locked_timed(&target_bo_gem->bo, time.tv_sec);
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}
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bo_gem->softpin_target_count = 0;
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pthread_mutex_unlock(&bufmgr_gem->lock);
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}
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@ -2080,7 +2169,7 @@ drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
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drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
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int i;
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if (bo_gem->relocs == NULL)
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if (bo_gem->relocs == NULL && bo_gem->softpin_target == NULL)
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return;
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for (i = 0; i < bo_gem->reloc_count; i++) {
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@ -2101,6 +2190,17 @@ drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
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/* Add the target to the validate list */
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drm_intel_add_validate_buffer2(target_bo, need_fence);
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}
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for (i = 0; i < bo_gem->softpin_target_count; i++) {
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drm_intel_bo *target_bo = bo_gem->softpin_target[i];
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if (target_bo == bo)
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continue;
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drm_intel_gem_bo_mark_mmaps_incoherent(bo);
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drm_intel_gem_bo_process_reloc2(target_bo);
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drm_intel_add_validate_buffer2(target_bo, false);
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}
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}
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@ -2138,12 +2238,14 @@ drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
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/* Update the buffer offset */
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if (bufmgr_gem->exec2_objects[i].offset != bo->offset64) {
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DBG("BO %d (%s) migrated: 0x%08x %08x -> 0x%08x %08x\n",
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/* If we're seeing softpinned object here it means that the kernel
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* has relocated our object... Indicating a programming error
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*/
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assert(!bo_gem->is_softpin);
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DBG("BO %d (%s) migrated: 0x%016llx -> 0x%016llx\n",
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bo_gem->gem_handle, bo_gem->name,
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upper_32_bits(bo->offset64),
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lower_32_bits(bo->offset64),
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upper_32_bits(bufmgr_gem->exec2_objects[i].offset),
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lower_32_bits(bufmgr_gem->exec2_objects[i].offset));
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(unsigned long long) bo->offset64,
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(unsigned long long) bufmgr_gem->exec2_objects[i].offset);
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bo->offset64 = bufmgr_gem->exec2_objects[i].offset;
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bo->offset = bufmgr_gem->exec2_objects[i].offset;
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}
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@ -2465,6 +2567,17 @@ drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
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return 0;
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}
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static int
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drm_intel_gem_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset)
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{
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drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
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bo_gem->is_softpin = true;
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bo->offset64 = offset;
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bo->offset = offset;
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return 0;
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}
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drm_intel_bo *
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drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int size)
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{
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@ -2844,6 +2957,13 @@ _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
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return 1;
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}
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for (i = 0; i< bo_gem->softpin_target_count; i++) {
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if (bo_gem->softpin_target[i] == target_bo)
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return 1;
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if (_drm_intel_gem_bo_references(bo_gem->softpin_target[i], target_bo))
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return 1;
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}
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return 0;
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}
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@ -3300,6 +3420,11 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
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ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
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bufmgr_gem->has_vebox = (ret == 0) & (*gp.value > 0);
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gp.param = I915_PARAM_HAS_EXEC_SOFTPIN;
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ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
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if (ret == 0 && *gp.value > 0)
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bufmgr_gem->bufmgr.bo_set_softpin_offset = drm_intel_gem_bo_set_softpin_offset;
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if (bufmgr_gem->gen < 4) {
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gp.param = I915_PARAM_NUM_FENCES_AVAIL;
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gp.value = &bufmgr_gem->available_fences;
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@ -240,6 +240,13 @@ struct _drm_intel_bufmgr {
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int (*bo_get_tiling) (drm_intel_bo *bo, uint32_t * tiling_mode,
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uint32_t * swizzle_mode);
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/**
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* Set the offset at which this buffer will be softpinned
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* \param bo Buffer to set the softpin offset for
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* \param offset Softpin offset
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*/
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int (*bo_set_softpin_offset) (drm_intel_bo *bo, uint64_t offset);
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/**
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* Create a visible name for a buffer which can be used by other apps
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*
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