tests/amdgpu: add memset dispatch test
add memset dispatch test for gfx9 v2: disable dispatch test for other ASICs Signed-off-by: Flora Cui <flora.cui@amd.com> Tested-by: Rui Teng <rui.teng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>main
Cui, Flora
Alex Deucher
parent
8c6dbd7938
commit
8db4e2db41
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@ -440,6 +440,11 @@ static void amdgpu_disable_suites()
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if (family_id < AMDGPU_FAMILY_VI || family_id > AMDGPU_FAMILY_RV)
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if (amdgpu_set_test_active(BASIC_TESTS_STR, "Sync dependency Test", CU_FALSE))
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fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
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/* This test was ran on GFX9 only */
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if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
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if (amdgpu_set_test_active(BASIC_TESTS_STR, "Dispatch Test", CU_FALSE))
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fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
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}
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/* The main() function for setting up and running the tests.
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@ -49,6 +49,7 @@ static void amdgpu_userptr_test(void);
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static void amdgpu_semaphore_test(void);
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static void amdgpu_sync_dependency_test(void);
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static void amdgpu_bo_eviction_test(void);
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static void amdgpu_dispatch_test(void);
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static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
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static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
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@ -70,6 +71,7 @@ CU_TestInfo basic_tests[] = {
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{ "Command submission Test (SDMA)", amdgpu_command_submission_sdma },
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{ "SW semaphore Test", amdgpu_semaphore_test },
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{ "Sync dependency Test", amdgpu_sync_dependency_test },
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{ "Dispatch Test", amdgpu_dispatch_test },
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CU_TEST_INFO_NULL,
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};
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#define BUFFER_SIZE (8 * 1024)
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@ -117,6 +119,7 @@ CU_TestInfo basic_tests[] = {
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#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
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(((op) & 0xFF) << 8) | \
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((n) & 0x3FFF) << 16)
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#define PACKET3_COMPUTE(op, n) PACKET3(op, n) | (1 << 1)
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/* Packet 3 types */
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#define PACKET3_NOP 0x10
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@ -245,8 +248,11 @@ CU_TestInfo basic_tests[] = {
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#define PACKET3_SET_SH_REG_START 0x00002c00
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#define PACKET3_DISPATCH_DIRECT 0x15
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#define PACKET3_EVENT_WRITE 0x46
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#define PACKET3_ACQUIRE_MEM 0x58
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#define PACKET3_SET_CONTEXT_REG 0x69
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#define PACKET3_SET_UCONFIG_REG 0x79
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#define PACKET3_DRAW_INDEX_AUTO 0x2D
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/* gfx 8 */
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#define mmCOMPUTE_PGM_LO 0x2e0c
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#define mmCOMPUTE_PGM_RSRC1 0x2e12
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@ -286,6 +292,25 @@ static uint32_t shader_bin[] = {
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#define CODE_OFFSET 512
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#define DATA_OFFSET 1024
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enum cs_type {
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CS_BUFFERCLEAR,
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};
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static const uint32_t bufferclear_cs_shader_gfx9[] = {
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0xD1FD0000, 0x04010C08, 0x7E020204, 0x7E040205,
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0x7E060206, 0x7E080207, 0xE01C2000, 0x80000100,
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0xBF810000
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};
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static const uint32_t bufferclear_cs_shader_registers_gfx9[][2] = {
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{0x2e12, 0x000C0041}, //{ mmCOMPUTE_PGM_RSRC1, 0x000C0041 },
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{0x2e13, 0x00000090}, //{ mmCOMPUTE_PGM_RSRC2, 0x00000090 },
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{0x2e07, 0x00000040}, //{ mmCOMPUTE_NUM_THREAD_X, 0x00000040 },
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{0x2e08, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Y, 0x00000001 },
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{0x2e09, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Z, 0x00000001 }
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};
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static const uint32_t bufferclear_cs_shader_registers_num_gfx9 = 5;
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int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size,
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unsigned alignment, unsigned heap, uint64_t alloc_flags,
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@ -1883,3 +1908,247 @@ static void amdgpu_sync_dependency_test(void)
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free(ibs_request.dependencies);
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}
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static int amdgpu_dispatch_load_cs_shader(uint8_t *ptr,
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int cs_type)
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{
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uint32_t shader_size;
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const uint32_t *shader;
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switch (cs_type) {
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case CS_BUFFERCLEAR:
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shader = bufferclear_cs_shader_gfx9;
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shader_size = sizeof(bufferclear_cs_shader_gfx9);
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break;
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default:
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return -1;
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break;
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}
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memcpy(ptr, shader, shader_size);
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return 0;
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}
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static int amdgpu_dispatch_init(uint32_t *ptr, uint32_t ip_type)
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{
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int i = 0;
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/* Write context control and load shadowing register if necessary */
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if (ip_type == AMDGPU_HW_IP_GFX) {
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ptr[i++] = PACKET3(PKT3_CONTEXT_CONTROL, 1);
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ptr[i++] = 0x80000000;
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ptr[i++] = 0x80000000;
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}
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/* Issue commands to set default compute state. */
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/* clear mmCOMPUTE_START_Z - mmCOMPUTE_START_X */
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ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 3);
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ptr[i++] = 0x204;
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i += 3;
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/* clear mmCOMPUTE_RESOURCE_LIMITS */
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ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
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ptr[i++] = 0x215;
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ptr[i++] = 0;
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/* clear mmCOMPUTE_TMPRING_SIZE */
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ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
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ptr[i++] = 0x218;
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ptr[i++] = 0;
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return i;
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}
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static int amdgpu_dispatch_write_cumask(uint32_t *ptr)
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{
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int i = 0;
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/* Issue commands to set cu mask used in current dispatch */
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/* set mmCOMPUTE_STATIC_THREAD_MGMT_SE1 - mmCOMPUTE_STATIC_THREAD_MGMT_SE0 */
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ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2);
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ptr[i++] = 0x216;
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ptr[i++] = 0xffffffff;
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ptr[i++] = 0xffffffff;
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/* set mmCOMPUTE_STATIC_THREAD_MGMT_SE3 - mmCOMPUTE_STATIC_THREAD_MGMT_SE2 */
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ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2);
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ptr[i++] = 0x219;
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ptr[i++] = 0xffffffff;
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ptr[i++] = 0xffffffff;
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return i;
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}
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static int amdgpu_dispatch_write2hw(uint32_t *ptr, uint64_t shader_addr)
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{
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int i, j;
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i = 0;
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/* Writes shader state to HW */
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/* set mmCOMPUTE_PGM_HI - mmCOMPUTE_PGM_LO */
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ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2);
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ptr[i++] = 0x20c;
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ptr[i++] = (shader_addr >> 8);
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ptr[i++] = (shader_addr >> 40);
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/* write sh regs*/
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for (j = 0; j < bufferclear_cs_shader_registers_num_gfx9; j++) {
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ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
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/* - Gfx9ShRegBase */
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ptr[i++] = bufferclear_cs_shader_registers_gfx9[j][0] - 0x2c00;
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ptr[i++] = bufferclear_cs_shader_registers_gfx9[j][1];
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}
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return i;
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}
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static void amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
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uint32_t ip_type,
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uint32_t ring)
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{
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amdgpu_context_handle context_handle;
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amdgpu_bo_handle bo_dst, bo_shader, bo_cmd, resources[3];
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volatile unsigned char *ptr_dst;
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void *ptr_shader;
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uint32_t *ptr_cmd;
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uint64_t mc_address_dst, mc_address_shader, mc_address_cmd;
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amdgpu_va_handle va_dst, va_shader, va_cmd;
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int i, r;
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int bo_dst_size = 16384;
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int bo_shader_size = 4096;
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int bo_cmd_size = 4096;
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struct amdgpu_cs_request ibs_request = {0};
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struct amdgpu_cs_ib_info ib_info= {0};
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amdgpu_bo_list_handle bo_list;
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struct amdgpu_cs_fence fence_status = {0};
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uint32_t expired;
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r = amdgpu_cs_ctx_create(device_handle, &context_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_alloc_and_map(device_handle, bo_cmd_size, 4096,
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AMDGPU_GEM_DOMAIN_GTT, 0,
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&bo_cmd, (void **)&ptr_cmd,
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&mc_address_cmd, &va_cmd);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
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AMDGPU_GEM_DOMAIN_VRAM, 0,
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&bo_shader, &ptr_shader,
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&mc_address_shader, &va_shader);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCLEAR);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
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AMDGPU_GEM_DOMAIN_VRAM, 0,
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&bo_dst, (void **)&ptr_dst,
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&mc_address_dst, &va_dst);
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CU_ASSERT_EQUAL(r, 0);
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i = 0;
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i += amdgpu_dispatch_init(ptr_cmd + i, ip_type);
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/* Issue commands to set cu mask used in current dispatch */
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i += amdgpu_dispatch_write_cumask(ptr_cmd + i);
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/* Writes shader state to HW */
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i += amdgpu_dispatch_write2hw(ptr_cmd + i, mc_address_shader);
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/* Write constant data */
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/* Writes the UAV constant data to the SGPRs. */
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ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
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ptr_cmd[i++] = 0x240;
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ptr_cmd[i++] = mc_address_dst;
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ptr_cmd[i++] = (mc_address_dst >> 32) | 0x100000;
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ptr_cmd[i++] = 0x400;
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ptr_cmd[i++] = 0x74fac;
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/* Sets a range of pixel shader constants */
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ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
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ptr_cmd[i++] = 0x244;
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ptr_cmd[i++] = 0x22222222;
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ptr_cmd[i++] = 0x22222222;
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ptr_cmd[i++] = 0x22222222;
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ptr_cmd[i++] = 0x22222222;
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/* dispatch direct command */
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ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
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ptr_cmd[i++] = 0x10;
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ptr_cmd[i++] = 1;
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ptr_cmd[i++] = 1;
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ptr_cmd[i++] = 1;
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while (i & 7)
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ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
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resources[0] = bo_dst;
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resources[1] = bo_shader;
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resources[2] = bo_cmd;
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r = amdgpu_bo_list_create(device_handle, 3, resources, NULL, &bo_list);
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CU_ASSERT_EQUAL(r, 0);
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ib_info.ib_mc_address = mc_address_cmd;
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ib_info.size = i;
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ibs_request.ip_type = ip_type;
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ibs_request.ring = ring;
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ibs_request.resources = bo_list;
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ibs_request.number_of_ibs = 1;
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ibs_request.ibs = &ib_info;
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ibs_request.fence_info.handle = NULL;
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/* submit CS */
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r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_list_destroy(bo_list);
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CU_ASSERT_EQUAL(r, 0);
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fence_status.ip_type = ip_type;
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fence_status.ip_instance = 0;
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fence_status.ring = ring;
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fence_status.context = context_handle;
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fence_status.fence = ibs_request.seq_no;
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/* wait for IB accomplished */
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r = amdgpu_cs_query_fence_status(&fence_status,
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AMDGPU_TIMEOUT_INFINITE,
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0, &expired);
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CU_ASSERT_EQUAL(r, 0);
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CU_ASSERT_EQUAL(expired, true);
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/* verify if memset test result meets with expected */
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i = 0;
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while(i < bo_dst_size) {
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CU_ASSERT_EQUAL(ptr_dst[i++], 0x22);
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}
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r = amdgpu_bo_unmap_and_free(bo_dst, va_dst, mc_address_dst, bo_dst_size);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_unmap_and_free(bo_shader, va_shader, mc_address_shader, bo_shader_size);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_unmap_and_free(bo_cmd, va_cmd, mc_address_cmd, bo_cmd_size);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_cs_ctx_free(context_handle);
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CU_ASSERT_EQUAL(r, 0);
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}
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static void amdgpu_dispatch_test(void)
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{
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int r;
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struct drm_amdgpu_info_hw_ip info;
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uint32_t ring_id;
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r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_COMPUTE, 0, &info);
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CU_ASSERT_EQUAL(r, 0);
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for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++)
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amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_COMPUTE, ring_id);
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r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
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CU_ASSERT_EQUAL(r, 0);
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for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++)
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amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_GFX, ring_id);
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}
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