parent
f803a45e74
commit
9270d984cd
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@ -50,6 +50,15 @@ extern "C" {
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#define MSM_PIPE_2D1 0x02
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#define MSM_PIPE_2D1 0x02
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#define MSM_PIPE_3D0 0x10
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#define MSM_PIPE_3D0 0x10
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/* The pipe-id just uses the lower bits, so can be OR'd with flags in
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* the upper 16 bits (which could be extended further, if needed, maybe
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* we extend/overload the pipe-id some day to deal with multiple rings,
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* but even then I don't think we need the full lower 16 bits).
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*/
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#define MSM_PIPE_ID_MASK 0xffff
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#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK)
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#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK)
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/* timeouts are specified in clock-monotonic absolute times (to simplify
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/* timeouts are specified in clock-monotonic absolute times (to simplify
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* restarting interrupted ioctls). The following struct is logically the
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* restarting interrupted ioctls). The following struct is logically the
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* same as 'struct timespec' but 32/64b ABI safe.
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* same as 'struct timespec' but 32/64b ABI safe.
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@ -183,17 +192,28 @@ struct drm_msm_gem_submit_bo {
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__u64 presumed; /* in/out, presumed buffer address */
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__u64 presumed; /* in/out, presumed buffer address */
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};
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};
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/* Valid submit ioctl flags: */
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#define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */
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#define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */
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#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */
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#define MSM_SUBMIT_FLAGS ( \
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MSM_SUBMIT_NO_IMPLICIT | \
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MSM_SUBMIT_FENCE_FD_IN | \
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MSM_SUBMIT_FENCE_FD_OUT | \
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0)
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/* Each cmdstream submit consists of a table of buffers involved, and
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/* Each cmdstream submit consists of a table of buffers involved, and
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* one or more cmdstream buffers. This allows for conditional execution
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* one or more cmdstream buffers. This allows for conditional execution
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* (context-restore), and IB buffers needed for per tile/bin draw cmds.
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* (context-restore), and IB buffers needed for per tile/bin draw cmds.
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*/
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*/
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struct drm_msm_gem_submit {
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struct drm_msm_gem_submit {
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__u32 pipe; /* in, MSM_PIPE_x */
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__u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */
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__u32 fence; /* out */
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__u32 fence; /* out */
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__u32 nr_bos; /* in, number of submit_bo's */
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__u32 nr_bos; /* in, number of submit_bo's */
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__u32 nr_cmds; /* in, number of submit_cmd's */
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__u32 nr_cmds; /* in, number of submit_cmd's */
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__u64 __user bos; /* in, ptr to array of submit_bo's */
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__u64 __user bos; /* in, ptr to array of submit_bo's */
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__u64 __user cmds; /* in, ptr to array of submit_cmd's */
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__u64 __user cmds; /* in, ptr to array of submit_cmd's */
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__s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
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};
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};
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/* The normal way to synchronize with the GPU is just to CPU_PREP on
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/* The normal way to synchronize with the GPU is just to CPU_PREP on
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@ -399,7 +399,7 @@ static int msm_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t *last_start
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{
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{
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struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring);
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struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring);
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struct drm_msm_gem_submit req = {
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struct drm_msm_gem_submit req = {
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.pipe = to_msm_pipe(ring->pipe)->pipe,
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.flags = to_msm_pipe(ring->pipe)->pipe,
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};
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};
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uint32_t i;
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uint32_t i;
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int ret;
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int ret;
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