amdgpu: cleanup VA IOCTL handling
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>main
parent
804048ff65
commit
933091e1d6
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@ -56,7 +56,7 @@ static void amdgpu_close_kms_handle(amdgpu_device_handle dev,
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static int amdgpu_bo_map(amdgpu_bo_handle bo, uint32_t alignment)
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static int amdgpu_bo_map(amdgpu_bo_handle bo, uint32_t alignment)
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{
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{
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amdgpu_device_handle dev = bo->dev;
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amdgpu_device_handle dev = bo->dev;
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union drm_amdgpu_gem_va va;
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struct drm_amdgpu_gem_va va;
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int r;
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int r;
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memset(&va, 0, sizeof(va));
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memset(&va, 0, sizeof(va));
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@ -67,17 +67,17 @@ static int amdgpu_bo_map(amdgpu_bo_handle bo, uint32_t alignment)
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if (bo->virtual_mc_base_address == AMDGPU_INVALID_VA_ADDRESS)
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if (bo->virtual_mc_base_address == AMDGPU_INVALID_VA_ADDRESS)
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return -ENOSPC;
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return -ENOSPC;
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va.in.handle = bo->handle;
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va.handle = bo->handle;
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va.in.operation = AMDGPU_VA_OP_MAP;
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va.operation = AMDGPU_VA_OP_MAP;
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va.in.flags = AMDGPU_VM_PAGE_READABLE |
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va.flags = AMDGPU_VM_PAGE_READABLE |
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AMDGPU_VM_PAGE_WRITEABLE |
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AMDGPU_VM_PAGE_WRITEABLE |
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AMDGPU_VM_PAGE_EXECUTABLE;
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AMDGPU_VM_PAGE_EXECUTABLE;
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va.in.va_address = bo->virtual_mc_base_address;
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va.va_address = bo->virtual_mc_base_address;
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va.in.offset_in_bo = 0;
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va.offset_in_bo = 0;
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va.in.map_size = ALIGN(bo->alloc_size, getpagesize());
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va.map_size = ALIGN(bo->alloc_size, getpagesize());
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r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_VA, &va, sizeof(va));
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r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_VA, &va, sizeof(va));
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if (r || va.out.result == AMDGPU_VA_RESULT_ERROR) {
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if (r) {
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amdgpu_bo_free_internal(bo);
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amdgpu_bo_free_internal(bo);
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return r;
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return r;
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}
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}
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@ -89,7 +89,7 @@ static int amdgpu_bo_map(amdgpu_bo_handle bo, uint32_t alignment)
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static void amdgpu_bo_unmap(amdgpu_bo_handle bo)
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static void amdgpu_bo_unmap(amdgpu_bo_handle bo)
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{
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{
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amdgpu_device_handle dev = bo->dev;
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amdgpu_device_handle dev = bo->dev;
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union drm_amdgpu_gem_va va;
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struct drm_amdgpu_gem_va va;
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int r;
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int r;
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if (bo->virtual_mc_base_address == AMDGPU_INVALID_VA_ADDRESS)
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if (bo->virtual_mc_base_address == AMDGPU_INVALID_VA_ADDRESS)
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@ -97,17 +97,17 @@ static void amdgpu_bo_unmap(amdgpu_bo_handle bo)
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memset(&va, 0, sizeof(va));
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memset(&va, 0, sizeof(va));
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va.in.handle = bo->handle;
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va.handle = bo->handle;
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va.in.operation = AMDGPU_VA_OP_UNMAP;
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va.operation = AMDGPU_VA_OP_UNMAP;
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va.in.flags = AMDGPU_VM_PAGE_READABLE |
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va.flags = AMDGPU_VM_PAGE_READABLE |
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AMDGPU_VM_PAGE_WRITEABLE |
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AMDGPU_VM_PAGE_WRITEABLE |
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AMDGPU_VM_PAGE_EXECUTABLE;
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AMDGPU_VM_PAGE_EXECUTABLE;
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va.in.va_address = bo->virtual_mc_base_address;
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va.va_address = bo->virtual_mc_base_address;
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va.in.offset_in_bo = 0;
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va.offset_in_bo = 0;
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va.in.map_size = ALIGN(bo->alloc_size, getpagesize());
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va.map_size = ALIGN(bo->alloc_size, getpagesize());
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r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_VA, &va, sizeof(va));
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r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_VA, &va, sizeof(va));
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if (r || va.out.result == AMDGPU_VA_RESULT_ERROR) {
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if (r) {
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fprintf(stderr, "amdgpu: VA_OP_UNMAP failed with %d\n", r);
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fprintf(stderr, "amdgpu: VA_OP_UNMAP failed with %d\n", r);
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return;
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return;
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}
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}
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@ -55,7 +55,7 @@
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#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
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#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
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#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
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#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
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#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
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#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
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#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, union drm_amdgpu_gem_va)
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#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
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#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
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#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
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#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
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#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
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#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
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#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
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@ -290,10 +290,6 @@ struct drm_amdgpu_gem_op {
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#define AMDGPU_VA_OP_MAP 1
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#define AMDGPU_VA_OP_MAP 1
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#define AMDGPU_VA_OP_UNMAP 2
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#define AMDGPU_VA_OP_UNMAP 2
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#define AMDGPU_VA_RESULT_OK 0
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#define AMDGPU_VA_RESULT_ERROR 1
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#define AMDGPU_VA_RESULT_VA_INVALID_ALIGNMENT 2
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/* Mapping flags */
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/* Mapping flags */
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/* readable mapping */
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/* readable mapping */
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#define AMDGPU_VM_PAGE_READABLE (1 << 1)
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#define AMDGPU_VM_PAGE_READABLE (1 << 1)
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@ -302,7 +298,7 @@ struct drm_amdgpu_gem_op {
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/* executable mapping, new for VI */
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/* executable mapping, new for VI */
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#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
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#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
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struct drm_amdgpu_gem_va_in {
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struct drm_amdgpu_gem_va {
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/* GEM object handle */
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/* GEM object handle */
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uint32_t handle;
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uint32_t handle;
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uint32_t _pad;
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uint32_t _pad;
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@ -319,16 +315,6 @@ struct drm_amdgpu_gem_va_in {
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uint64_t map_size;
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uint64_t map_size;
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};
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};
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struct drm_amdgpu_gem_va_out {
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uint32_t result;
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uint32_t _pad;
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};
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union drm_amdgpu_gem_va {
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struct drm_amdgpu_gem_va_in in;
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struct drm_amdgpu_gem_va_out out;
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};
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#define AMDGPU_HW_IP_GFX 0
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#define AMDGPU_HW_IP_GFX 0
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#define AMDGPU_HW_IP_COMPUTE 1
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#define AMDGPU_HW_IP_COMPUTE 1
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#define AMDGPU_HW_IP_DMA 2
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#define AMDGPU_HW_IP_DMA 2
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