Reworked the jump-code in via_dma.c. The command regulator now seems to
pause correctly after a jump. Removed the debug message from within the
interrupt handler of via_irq.c
main
Thomas Hellstrom
parent
08758b2fb7
commit
9409d8231c
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@ -8,14 +8,17 @@
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* Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
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* All Rights Reserved.
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*
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* Copyright 2004 The Unichrome project.
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* All Rights Reserved.
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*
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**************************************************************************/
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#include "drmP.h"
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#include "drm.h"
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#include "via_drm.h"
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#include "via_drv.h"
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#include "via_3d_reg.h"
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#define VIA_2D_CMD 0xF0000000
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#define via_flush_write_combine() DRM_MEMORYBARRIER()
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#define VIA_OUT_RING_QW(w1,w2) \
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@ -61,12 +64,12 @@ static int via_check_command_stream(const uint32_t * buf, unsigned int size)
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for (i = 0; i < size; ++i) {
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offset = *buf;
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buf += 2;
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if ((offset > ((0x3FF >> 2) | VIA_2D_CMD)) &&
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(offset < ((0xC00 >> 2) | VIA_2D_CMD))) {
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if ((offset > ((0x3FF >> 2) | HALCYON_HEADER1)) &&
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(offset < ((0xC00 >> 2) | HALCYON_HEADER1))) {
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DRM_ERROR
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("Attempt to access Burst Command / 3D Area.\n");
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return DRM_ERR(EINVAL);
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} else if (offset > ((0xDFF >> 2) | VIA_2D_CMD)) {
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} else if (offset > ((0xDFF >> 2) | HALCYON_HEADER1)) {
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DRM_ERROR("Attempt to access DMA or VGA registers.\n");
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return DRM_ERR(EINVAL);
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}
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@ -291,7 +294,7 @@ static int via_parse_pci_cmdbuffer(drm_device_t * dev, const char *buf,
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size >>= 3;
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for (i = 0; i < size; ++i) {
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offset = (*regbuf++ & ~VIA_2D_CMD) << 2;
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offset = (*regbuf++ & ~HALCYON_HEADER1) << 2;
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value = *regbuf++;
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VIA_WRITE(offset, value);
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}
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@ -356,7 +359,6 @@ int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
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}
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/************************************************************************/
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#include "via_3d_reg.h"
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#define CMDBUF_ALIGNMENT_SIZE (0x100)
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#define CMDBUF_ALIGNMENT_MASK (0xff)
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@ -373,7 +375,7 @@ int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
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#define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */
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#define SetReg2DAGP(nReg, nData) { \
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*((uint32_t *)(vb)) = ((nReg) >> 2) | 0xF0000000; \
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*((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \
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*((uint32_t *)(vb) + 1) = (nData); \
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vb = ((uint32_t *)vb) + 2; \
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dev_priv->dma_low +=8; \
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@ -534,106 +536,47 @@ static void via_cmdbuf_start(drm_via_private_t * dev_priv)
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static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
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{
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uint32_t *vb = via_get_dma(dev_priv);
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/* GEDST */
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SetReg2DAGP(0x0C, (0 | (0 << 16)));
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/* GEWD */
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SetReg2DAGP(0x10, 0 | (0 << 16));
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/* BITBLT */
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SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
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}
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static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
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{
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uint32_t agp_base;
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uint32_t pause_addr, pause_addr_lo, pause_addr_hi;
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uint32_t start_addr;
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uint32_t end_addr, end_addr_lo;
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uint32_t *vb;
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uint32_t qw_pad_count;
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uint32_t command;
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uint32_t jump_addr, jump_addr_lo, jump_addr_hi;
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/* Seems like Unichrome has bug that when the PAUSE register is
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* set in the AGP command stream immediately after a PCI write to
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* the same register, the command regulator goes into a looping
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* state. Prepending a BitBLT command to stall the command
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* regulator for a moment seems to solve the problem.
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*/
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via_cmdbuf_wait(dev_priv, 48);
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via_dummy_bitblt(dev_priv);
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via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE);
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/* At end of buffer, rewind with a JUMP command. */
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vb = via_get_dma(dev_priv);
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*vb++ = HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
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(VIA_REG_TRANSPACE >> 2);
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*vb++ = (HC_ParaType_PreCR << 16);
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dev_priv->dma_low += 8;
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qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
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((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
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uint32_t pause_addr_lo, pause_addr_hi;
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uint32_t jump_addr_lo, jump_addr_hi;
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volatile uint32_t *last_pause_ptr;
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agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
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start_addr = agp_base;
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end_addr = agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
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via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
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&jump_addr_lo);
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jump_addr = end_addr;
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jump_addr_lo = ((HC_SubA_HAGPBpL << 24) | HC_HAGPBpID_JUMP |
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(jump_addr & 0xffffff));
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jump_addr_hi = ((HC_SubA_HAGPBpH << 24) | (jump_addr >> 24));
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end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
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command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
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((end_addr & 0xff000000) >> 16));
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*vb++ = command;
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*vb++ = end_addr_lo;
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dev_priv->dma_low += 8;
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vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
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/* Now at beginning of buffer, make sure engine will pause here. */
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dev_priv->dma_low = 0;
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if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) {
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DRM_ERROR("via_cmdbuf_jump failed\n");
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}
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vb = via_get_dma(dev_priv);
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end_addr = agp_base + dev_priv->dma_high;
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/*
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* The command regulator needs to stall for a while since it probably
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* had a concussion during the jump... It will stall at the second
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* bitblt since the 2D engine is busy with the first.
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*/
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end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
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command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
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((end_addr & 0xff000000) >> 16));
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via_dummy_bitblt(dev_priv);
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via_dummy_bitblt(dev_priv);
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last_pause_ptr = via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
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&pause_addr_lo) -1;
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qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
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((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
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/*
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* The regulator may still be suffering from the shock of the jump.
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* Add another pause command to make sure it really will get itself together
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* and pause.
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*/
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pause_addr = agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
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pause_addr_lo = ((HC_SubA_HAGPBpL << 24) | HC_HAGPBpID_PAUSE |
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(pause_addr & 0xffffff));
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pause_addr_hi = ((HC_SubA_HAGPBpH << 24) | (pause_addr >> 24));
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*vb++ = HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
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(VIA_REG_TRANSPACE >> 2);
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*vb++ = (HC_ParaType_PreCR << 16);
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dev_priv->dma_low += 8;
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*vb++ = pause_addr_hi;
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*vb++ = pause_addr_lo;
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dev_priv->dma_low += 8;
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*vb++ = command;
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*vb++ = end_addr_lo;
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dev_priv->dma_low += 8;
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vb = via_align_buffer(dev_priv, vb, qw_pad_count - 4);
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*vb++ = pause_addr_hi;
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*vb++ = pause_addr_lo;
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dev_priv->dma_low += 8;
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via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
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&pause_addr_lo);
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*last_pause_ptr = pause_addr_lo;
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via_hook_segment( dev_priv, jump_addr_hi, jump_addr_lo, 0);
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}
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@ -641,9 +584,7 @@ static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
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static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)
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{
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/* via_cmdbuf_jump(dev_priv); */
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via_cmdbuf_reset(dev_priv);
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via_cmdbuf_start(dev_priv);
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via_cmdbuf_jump(dev_priv);
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}
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static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)
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@ -28,11 +28,11 @@
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#define DRIVER_NAME "via"
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#define DRIVER_DESC "VIA Unichrome"
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#define DRIVER_DATE "20041030"
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#define DRIVER_DATE "20041101"
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#define DRIVER_MAJOR 2
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#define DRIVER_MINOR 0
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#define DRIVER_PATCHLEVEL 2
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#define DRIVER_PATCHLEVEL 3
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typedef struct drm_via_ring_buffer {
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drm_map_t map;
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@ -53,7 +53,6 @@ irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
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int handled = 0;
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status = VIA_READ(VIA_REG_INTERRUPT);
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DRM_DEBUG("viadrv_irq_handler Status: %x\n", status);
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if (status & VIA_IRQ_VBI_PENDING) {
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atomic_inc(&dev->vbl_received);
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DRM_WAKEUP(&dev->vbl_queue);
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@ -30,11 +30,11 @@
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#define DRIVER_NAME "via"
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#define DRIVER_DESC "VIA Unichrome"
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#define DRIVER_DATE "20041030"
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#define DRIVER_DATE "20041101"
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#define DRIVER_MAJOR 2
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#define DRIVER_MINOR 0
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#define DRIVER_PATCHLEVEL 2
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#define DRIVER_PATCHLEVEL 3
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#define DRIVER_IOCTLS \
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[DRM_IOCTL_NR(DRM_IOCTL_VIA_ALLOCMEM)] = { via_mem_alloc, 1, 0 }, \
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123
shared/via_dma.c
123
shared/via_dma.c
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@ -8,6 +8,9 @@
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* Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
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* All Rights Reserved.
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*
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* Copyright 2004 The Unichrome project.
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* All Rights Reserved.
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*
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**************************************************************************/
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#include "via.h"
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@ -15,8 +18,8 @@
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#include "drm.h"
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#include "via_drm.h"
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#include "via_drv.h"
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#include "via_3d_reg.h"
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#define VIA_2D_CMD 0xF0000000
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#define via_flush_write_combine() DRM_MEMORYBARRIER()
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#define VIA_OUT_RING_QW(w1,w2) \
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@ -62,12 +65,12 @@ static int via_check_command_stream(const uint32_t * buf, unsigned int size)
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for (i = 0; i < size; ++i) {
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offset = *buf;
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buf += 2;
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if ((offset > ((0x3FF >> 2) | VIA_2D_CMD)) &&
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(offset < ((0xC00 >> 2) | VIA_2D_CMD))) {
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if ((offset > ((0x3FF >> 2) | HALCYON_HEADER1)) &&
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(offset < ((0xC00 >> 2) | HALCYON_HEADER1))) {
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DRM_ERROR
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("Attempt to access Burst Command / 3D Area.\n");
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return DRM_ERR(EINVAL);
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} else if (offset > ((0xDFF >> 2) | VIA_2D_CMD)) {
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} else if (offset > ((0xDFF >> 2) | HALCYON_HEADER1)) {
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DRM_ERROR("Attempt to access DMA or VGA registers.\n");
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return DRM_ERR(EINVAL);
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}
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@ -292,7 +295,7 @@ static int via_parse_pci_cmdbuffer(drm_device_t * dev, const char *buf,
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size >>= 3;
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for (i = 0; i < size; ++i) {
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offset = (*regbuf++ & ~VIA_2D_CMD) << 2;
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offset = (*regbuf++ & ~HALCYON_HEADER1) << 2;
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value = *regbuf++;
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VIA_WRITE(offset, value);
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}
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@ -357,7 +360,6 @@ int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
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}
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/************************************************************************/
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#include "via_3d_reg.h"
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#define CMDBUF_ALIGNMENT_SIZE (0x100)
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#define CMDBUF_ALIGNMENT_MASK (0xff)
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@ -374,7 +376,7 @@ int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
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#define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */
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#define SetReg2DAGP(nReg, nData) { \
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*((uint32_t *)(vb)) = ((nReg) >> 2) | 0xF0000000; \
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*((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \
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*((uint32_t *)(vb) + 1) = (nData); \
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vb = ((uint32_t *)vb) + 2; \
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dev_priv->dma_low +=8; \
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@ -535,11 +537,8 @@ static void via_cmdbuf_start(drm_via_private_t * dev_priv)
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static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
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{
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uint32_t *vb = via_get_dma(dev_priv);
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/* GEDST */
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SetReg2DAGP(0x0C, (0 | (0 << 16)));
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/* GEWD */
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SetReg2DAGP(0x10, 0 | (0 << 16));
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/* BITBLT */
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SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
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}
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@ -547,95 +546,39 @@ static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
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static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
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{
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uint32_t agp_base;
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uint32_t pause_addr, pause_addr_lo, pause_addr_hi;
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uint32_t start_addr;
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uint32_t end_addr, end_addr_lo;
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uint32_t *vb;
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uint32_t qw_pad_count;
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uint32_t command;
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uint32_t jump_addr, jump_addr_lo, jump_addr_hi;
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/* Seems like Unichrome has bug that when the PAUSE register is
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* set in the AGP command stream immediately after a PCI write to
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* the same register, the command regulator goes into a looping
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* state. Prepending a BitBLT command to stall the command
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* regulator for a moment seems to solve the problem.
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*/
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via_cmdbuf_wait(dev_priv, 48);
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via_dummy_bitblt(dev_priv);
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via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE);
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/* At end of buffer, rewind with a JUMP command. */
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vb = via_get_dma(dev_priv);
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*vb++ = HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
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(VIA_REG_TRANSPACE >> 2);
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*vb++ = (HC_ParaType_PreCR << 16);
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dev_priv->dma_low += 8;
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qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
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((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
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uint32_t pause_addr_lo, pause_addr_hi;
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uint32_t jump_addr_lo, jump_addr_hi;
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volatile uint32_t *last_pause_ptr;
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agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
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start_addr = agp_base;
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end_addr = agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
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via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
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&jump_addr_lo);
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jump_addr = end_addr;
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jump_addr_lo = ((HC_SubA_HAGPBpL << 24) | HC_HAGPBpID_JUMP |
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(jump_addr & 0xffffff));
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jump_addr_hi = ((HC_SubA_HAGPBpH << 24) | (jump_addr >> 24));
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end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
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command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
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((end_addr & 0xff000000) >> 16));
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*vb++ = command;
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*vb++ = end_addr_lo;
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dev_priv->dma_low += 8;
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vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
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/* Now at beginning of buffer, make sure engine will pause here. */
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dev_priv->dma_low = 0;
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if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) {
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DRM_ERROR("via_cmdbuf_jump failed\n");
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}
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vb = via_get_dma(dev_priv);
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end_addr = agp_base + dev_priv->dma_high;
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/*
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* The command regulator needs to stall for a while since it probably
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* had a concussion during the jump... It will stall at the second
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* bitblt since the 2D engine is busy with the first.
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*/
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end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
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command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
|
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((end_addr & 0xff000000) >> 16));
|
||||
via_dummy_bitblt(dev_priv);
|
||||
via_dummy_bitblt(dev_priv);
|
||||
last_pause_ptr = via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
|
||||
&pause_addr_lo) -1;
|
||||
|
||||
qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
|
||||
((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
|
||||
/*
|
||||
* The regulator may still be suffering from the shock of the jump.
|
||||
* Add another pause command to make sure it really will get itself together
|
||||
* and pause.
|
||||
*/
|
||||
|
||||
pause_addr = agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
|
||||
pause_addr_lo = ((HC_SubA_HAGPBpL << 24) | HC_HAGPBpID_PAUSE |
|
||||
(pause_addr & 0xffffff));
|
||||
pause_addr_hi = ((HC_SubA_HAGPBpH << 24) | (pause_addr >> 24));
|
||||
|
||||
*vb++ = HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
|
||||
(VIA_REG_TRANSPACE >> 2);
|
||||
*vb++ = (HC_ParaType_PreCR << 16);
|
||||
dev_priv->dma_low += 8;
|
||||
|
||||
*vb++ = pause_addr_hi;
|
||||
*vb++ = pause_addr_lo;
|
||||
dev_priv->dma_low += 8;
|
||||
|
||||
*vb++ = command;
|
||||
*vb++ = end_addr_lo;
|
||||
dev_priv->dma_low += 8;
|
||||
|
||||
vb = via_align_buffer(dev_priv, vb, qw_pad_count - 4);
|
||||
|
||||
*vb++ = pause_addr_hi;
|
||||
*vb++ = pause_addr_lo;
|
||||
dev_priv->dma_low += 8;
|
||||
via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
|
||||
&pause_addr_lo);
|
||||
*last_pause_ptr = pause_addr_lo;
|
||||
via_hook_segment( dev_priv, jump_addr_hi, jump_addr_lo, 0);
|
||||
}
|
||||
|
||||
|
|
@ -643,9 +586,7 @@ static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
|
|||
|
||||
static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)
|
||||
{
|
||||
/* via_cmdbuf_jump(dev_priv); */
|
||||
via_cmdbuf_reset(dev_priv);
|
||||
via_cmdbuf_start(dev_priv);
|
||||
via_cmdbuf_jump(dev_priv);
|
||||
}
|
||||
|
||||
static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)
|
||||
|
|
|
|||
|
|
@ -54,7 +54,6 @@ irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
|
|||
int handled = 0;
|
||||
|
||||
status = VIA_READ(VIA_REG_INTERRUPT);
|
||||
DRM_DEBUG("viadrv_irq_handler Status: %x\n", status);
|
||||
if (status & VIA_IRQ_VBI_PENDING) {
|
||||
atomic_inc(&dev->vbl_received);
|
||||
DRM_WAKEUP(&dev->vbl_queue);
|
||||
|
|
|
|||
Loading…
Reference in New Issue