diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index f8d9c87e..f7972343 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -134,8 +134,8 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev,
 	args.in.alignment = alloc_buffer->phys_alignment;
 
 	/* Set the placement. */
-	args.in.domains = heap & AMDGPU_GEM_DOMAIN_MASK;
-	args.in.domain_flags = alloc_buffer->flags & AMDGPU_GEM_CREATE_CPU_GTT_MASK;
+	args.in.domains = heap;
+	args.in.domain_flags = alloc_buffer->flags;
 
 	/* Allocate the buffer with the preferred heap. */
 	r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_CREATE,
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index dc4caf16..03e46b0d 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -67,8 +67,6 @@
 #define AMDGPU_GEM_DOMAIN_GWS		0x10
 #define AMDGPU_GEM_DOMAIN_OA		0x20
 
-#define AMDGPU_GEM_DOMAIN_MASK		0x3F
-
 /* Flag that CPU access will be required for the case of VRAM domain */
 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED	(1 << 0)
 /* Flag that CPU access will not work, this VRAM domain is invisible */
@@ -76,12 +74,6 @@
 /* Flag that USWC attributes should be used for GTT */
 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC		(1 << 2)
 
-/* Flag mask for GTT domain_flags */
-#define AMDGPU_GEM_CREATE_CPU_GTT_MASK \
-	(AMDGPU_GEM_CREATE_CPU_GTT_USWC | \
-	 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | \
-	 AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
-
 struct drm_amdgpu_gem_create_in  {
 	/** the requested memory size */
 	uint64_t bo_size;