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amdgpu: update_drm.h for new CTX OP to set/get stable pstates 

Based on agd5f/drm-next.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
main
Samuel Pitoiset 2021-12-31 08:54:34 +01:00
parent 63d06ad3c3
commit 94bc814416
1 changed files with 23 additions and 9 deletions
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32
include/drm/amdgpu_drm.h
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@ -80,7 +80,7 @@ extern "C" {
* *
* %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
* GPU's virtual address space via gart. Gart memory linearizes non-contiguous * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
* pages of system memory, allows GPU access system memory in a linezrized * pages of system memory, allows GPU access system memory in a linearized
* fashion. * fashion.
* *
* %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory
@ -206,6 +206,8 @@ union drm_amdgpu_bo_list {
#define AMDGPU_CTX_OP_FREE_CTX 2 #define AMDGPU_CTX_OP_FREE_CTX 2
#define AMDGPU_CTX_OP_QUERY_STATE 3 #define AMDGPU_CTX_OP_QUERY_STATE 3
#define AMDGPU_CTX_OP_QUERY_STATE2 4 #define AMDGPU_CTX_OP_QUERY_STATE2 4
#define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5
#define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6
/* GPU reset status */ /* GPU reset status */
#define AMDGPU_CTX_NO_RESET 0 #define AMDGPU_CTX_NO_RESET 0
@ -238,10 +240,18 @@ union drm_amdgpu_bo_list {
#define AMDGPU_CTX_PRIORITY_HIGH 512 #define AMDGPU_CTX_PRIORITY_HIGH 512
#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
/* select a stable profiling pstate for perfmon tools */
#define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf
#define AMDGPU_CTX_STABLE_PSTATE_NONE 0
#define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1
#define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2
#define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3
#define AMDGPU_CTX_STABLE_PSTATE_PEAK 4
struct drm_amdgpu_ctx_in { struct drm_amdgpu_ctx_in {
/** AMDGPU_CTX_OP_* */ /** AMDGPU_CTX_OP_* */
__u32 op; __u32 op;
/** For future use, no flags defined so far */ /** Flags */
__u32 flags; __u32 flags;
__u32 ctx_id; __u32 ctx_id;
/** AMDGPU_CTX_PRIORITY_* */ /** AMDGPU_CTX_PRIORITY_* */
@ -262,6 +272,11 @@ union drm_amdgpu_ctx_out {
/** Reset status since the last call of the ioctl. */ /** Reset status since the last call of the ioctl. */
__u32 reset_status; __u32 reset_status;
} state; } state;
struct {
__u32 flags;
__u32 _pad;
} pstate;
}; };
union drm_amdgpu_ctx { union drm_amdgpu_ctx {
@ -786,13 +801,6 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
/* query ras mask of enabled features*/ /* query ras mask of enabled features*/
#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
/* query video encode/decode caps */
#define AMDGPU_INFO_VIDEO_CAPS 0x21
/* Subquery id: Decode */
#define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
/* Subquery id: Encode */
#define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
/* RAS MASK: UMC (VRAM) */ /* RAS MASK: UMC (VRAM) */
#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
/* RAS MASK: SDMA */ /* RAS MASK: SDMA */
@ -821,6 +829,12 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
/* RAS MASK: FUSE */ /* RAS MASK: FUSE */
#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
/* query video encode/decode caps */
#define AMDGPU_INFO_VIDEO_CAPS 0x21
/* Subquery id: Decode */
#define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
/* Subquery id: Encode */
#define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff