amdgpu: cleanup public interface v2
Remove the mostly unused device parameter, for the few cases where we really need it keep a copy in the context structure. v2: rebased on internal branch Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>main
Christian König
Alex Deucher
parent
9c3bec246e
commit
9c2afffedb
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@ -882,7 +882,6 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
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*
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* Destroy GPU execution context when not needed any more
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*
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* \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
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* \param context - \c [in] GPU Context handle
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*
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* \return 0 on success\n
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@ -892,13 +891,11 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
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* \sa amdgpu_cs_ctx_create()
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*
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*/
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int amdgpu_cs_ctx_free(amdgpu_device_handle dev,
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amdgpu_context_handle context);
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int amdgpu_cs_ctx_free(amdgpu_context_handle context);
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/**
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* Query reset state for the specific GPU Context
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*
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* \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
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* \param context - \c [in] GPU Context handle
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* \param state - \c [out] Reset state status
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*
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@ -909,8 +906,7 @@ int amdgpu_cs_ctx_free(amdgpu_device_handle dev,
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* \sa amdgpu_cs_ctx_create()
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*
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*/
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int amdgpu_cs_query_reset_state(amdgpu_device_handle dev,
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amdgpu_context_handle context,
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int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
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enum amdgpu_cs_ctx_reset_state *state);
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@ -924,7 +920,6 @@ int amdgpu_cs_query_reset_state(amdgpu_device_handle dev,
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* Allocate memory to be filled with PM4 packets and be served as the first
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* entry point of execution (a.k.a. Indirect Buffer)
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*
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* \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
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* \param context - \c [in] GPU Context which will use IB
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* \param ib_size - \c [in] Size of allocation
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* \param output - \c [out] Pointer to structure to get information about
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@ -937,8 +932,7 @@ int amdgpu_cs_query_reset_state(amdgpu_device_handle dev,
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* \sa amdgpu_cs_free_ib()
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*
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*/
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int amdgpu_cs_alloc_ib(amdgpu_device_handle dev,
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amdgpu_context_handle context,
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int amdgpu_cs_alloc_ib(amdgpu_context_handle context,
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enum amdgpu_cs_ib_size ib_size,
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struct amdgpu_cs_ib_alloc_result *output);
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@ -946,8 +940,6 @@ int amdgpu_cs_alloc_ib(amdgpu_device_handle dev,
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* If UMD has allocates IBs which doesn’t need any more than those IBs must
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* be explicitly freed
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*
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* \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
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* \param context - \c [in] GPU Context containing IB
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* \param handle - \c [in] IB handle
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*
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* \return 0 on success\n
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@ -960,9 +952,7 @@ int amdgpu_cs_alloc_ib(amdgpu_device_handle dev,
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* \sa amdgpu_cs_alloc_ib()
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*
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*/
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int amdgpu_cs_free_ib(amdgpu_device_handle dev,
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amdgpu_context_handle context,
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amdgpu_ib_handle handle);
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int amdgpu_cs_free_ib(amdgpu_ib_handle handle);
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/**
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* Send request to submit command buffers to hardware.
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@ -1011,8 +1001,7 @@ int amdgpu_cs_free_ib(amdgpu_device_handle dev,
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* amdgpu_cs_query_fence_status()
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*
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*/
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int amdgpu_cs_submit(amdgpu_device_handle dev,
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amdgpu_context_handle context,
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int amdgpu_cs_submit(amdgpu_context_handle context,
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uint64_t flags,
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struct amdgpu_cs_request *ibs_request,
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uint32_t number_of_requests,
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@ -1038,8 +1027,7 @@ int amdgpu_cs_submit(amdgpu_device_handle dev,
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*
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* \sa amdgpu_cs_submit()
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*/
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int amdgpu_cs_query_fence_status(amdgpu_device_handle dev,
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struct amdgpu_cs_query_fence *fence,
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int amdgpu_cs_query_fence_status(struct amdgpu_cs_query_fence *fence,
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uint32_t *expired);
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@ -42,8 +42,7 @@
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*
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* \return 0 on success otherwise POSIX Error code
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*/
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static int amdgpu_cs_create_ib(amdgpu_device_handle dev,
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amdgpu_context_handle context,
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static int amdgpu_cs_create_ib(amdgpu_context_handle context,
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enum amdgpu_cs_ib_size ib_size,
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amdgpu_ib_handle *ib)
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{
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@ -79,7 +78,7 @@ static int amdgpu_cs_create_ib(amdgpu_device_handle dev,
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alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
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r = amdgpu_bo_alloc(dev,
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r = amdgpu_bo_alloc(context->dev,
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&alloc_buffer,
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&info);
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if (r)
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@ -98,6 +97,7 @@ static int amdgpu_cs_create_ib(amdgpu_device_handle dev,
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return -ENOMEM;
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}
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new_ib->context = context;
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new_ib->buf_handle = info.buf_handle;
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new_ib->cpu = cpu;
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new_ib->virtual_mc_base_address = info.virtual_mc_base_address;
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@ -114,10 +114,10 @@ static int amdgpu_cs_create_ib(amdgpu_device_handle dev,
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*
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* \return 0 on success otherwise POSIX Error code
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*/
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static int amdgpu_cs_destroy_ib(amdgpu_device_handle dev,
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amdgpu_ib_handle ib)
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static int amdgpu_cs_destroy_ib(amdgpu_ib_handle ib)
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{
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int r;
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r = amdgpu_bo_cpu_unmap(ib->buf_handle);
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if (r)
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return r;
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@ -162,8 +162,7 @@ static int amdgpu_cs_init_ib_pool(amdgpu_context_handle context)
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*
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* \return 0 on success otherwise POSIX Error code
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*/
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static int amdgpu_cs_alloc_from_ib_pool(amdgpu_device_handle dev,
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amdgpu_context_handle context,
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static int amdgpu_cs_alloc_from_ib_pool(amdgpu_context_handle context,
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enum amdgpu_cs_ib_size ib_size,
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amdgpu_ib_handle *ib)
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{
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@ -210,21 +209,19 @@ static void amdgpu_cs_free_to_ib_pool(amdgpu_context_handle context,
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*
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* \return 0 on success otherwise POSIX Error code
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*/
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static int amdgpu_cs_destroy_ib_pool(amdgpu_device_handle dev,
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amdgpu_context_handle context)
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static int amdgpu_cs_destroy_ib_pool(amdgpu_context_handle context)
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{
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int i;
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int r;
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struct list_head *head;
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struct amdgpu_ib *next;
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struct amdgpu_ib *storage;
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int i, r;
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r = 0;
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pthread_mutex_lock(&context->pool_mutex);
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for (i = 0; i < AMDGPU_CS_IB_SIZE_NUM; i++) {
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head = &context->ib_pools[i];
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LIST_FOR_EACH_ENTRY_SAFE(next, storage, head, list_node) {
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r = amdgpu_cs_destroy_ib(dev, next);
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r = amdgpu_cs_destroy_ib(next);
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if (r)
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break;
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}
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@ -268,8 +265,7 @@ static int amdgpu_cs_init_pendings(amdgpu_context_handle context)
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*
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* \return 0 on success otherwise POSIX Error code
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*/
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static int amdgpu_cs_destroy_pendings(amdgpu_device_handle dev,
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amdgpu_context_handle context)
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static int amdgpu_cs_destroy_pendings(amdgpu_context_handle context)
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{
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int ip, inst;
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uint32_t ring;
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@ -285,7 +281,7 @@ static int amdgpu_cs_destroy_pendings(amdgpu_device_handle dev,
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for (ring = 0; ring < AMDGPU_CS_MAX_RINGS; ring++) {
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head = &context->pendings[ip][inst][ring];
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LIST_FOR_EACH_ENTRY_SAFE(next, s, head, list_node) {
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r = amdgpu_cs_destroy_ib(dev, next);
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r = amdgpu_cs_destroy_ib(next);
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if (r)
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break;
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}
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@ -293,7 +289,7 @@ static int amdgpu_cs_destroy_pendings(amdgpu_device_handle dev,
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head = &context->freed;
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LIST_FOR_EACH_ENTRY_SAFE(next, s, head, list_node) {
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r = amdgpu_cs_destroy_ib(dev, next);
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r = amdgpu_cs_destroy_ib(next);
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if (r)
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break;
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}
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@ -441,39 +437,35 @@ static void amdgpu_cs_all_pending_gc(amdgpu_context_handle context)
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*
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* \return 0 on success otherwise POSIX Error code
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*/
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static int amdgpu_cs_alloc_ib_local(amdgpu_device_handle dev,
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amdgpu_context_handle context,
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static int amdgpu_cs_alloc_ib_local(amdgpu_context_handle context,
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enum amdgpu_cs_ib_size ib_size,
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amdgpu_ib_handle *ib)
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{
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int r;
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r = amdgpu_cs_alloc_from_ib_pool(dev, context, ib_size, ib);
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r = amdgpu_cs_alloc_from_ib_pool(context, ib_size, ib);
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if (!r)
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return r;
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amdgpu_cs_all_pending_gc(context);
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/* Retry to allocate from free IB pools after garbage collector. */
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r = amdgpu_cs_alloc_from_ib_pool(dev, context, ib_size, ib);
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r = amdgpu_cs_alloc_from_ib_pool(context, ib_size, ib);
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if (!r)
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return r;
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/* There is no suitable IB in free pools. Create one. */
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r = amdgpu_cs_create_ib(dev, context, ib_size, ib);
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r = amdgpu_cs_create_ib(context, ib_size, ib);
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return r;
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}
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int amdgpu_cs_alloc_ib(amdgpu_device_handle dev,
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amdgpu_context_handle context,
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int amdgpu_cs_alloc_ib(amdgpu_context_handle context,
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enum amdgpu_cs_ib_size ib_size,
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struct amdgpu_cs_ib_alloc_result *output)
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{
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int r;
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amdgpu_ib_handle ib;
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if (NULL == dev)
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return -EINVAL;
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if (NULL == context)
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return -EINVAL;
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if (NULL == output)
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@ -481,7 +473,7 @@ int amdgpu_cs_alloc_ib(amdgpu_device_handle dev,
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if (ib_size >= AMDGPU_CS_IB_SIZE_NUM)
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return -EINVAL;
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r = amdgpu_cs_alloc_ib_local(dev, context, ib_size, &ib);
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r = amdgpu_cs_alloc_ib_local(context, ib_size, &ib);
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if (!r) {
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output->handle = ib;
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output->cpu = ib->cpu;
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@ -491,17 +483,14 @@ int amdgpu_cs_alloc_ib(amdgpu_device_handle dev,
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return r;
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}
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int amdgpu_cs_free_ib(amdgpu_device_handle dev,
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amdgpu_context_handle context,
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amdgpu_ib_handle handle)
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int amdgpu_cs_free_ib(amdgpu_ib_handle handle)
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{
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if (NULL == dev)
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return -EINVAL;
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if (NULL == context)
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return -EINVAL;
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amdgpu_context_handle context;
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if (NULL == handle)
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return -EINVAL;
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context = handle->context;
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pthread_mutex_lock(&context->pendings_mutex);
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LIST_ADD(&handle->list_node, &context->freed);
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pthread_mutex_unlock(&context->pendings_mutex);
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@ -532,6 +521,8 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
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if (NULL == gpu_context)
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return -ENOMEM;
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gpu_context->dev = dev;
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r = pthread_mutex_init(&gpu_context->sequence_mutex, NULL);
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if (r)
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goto error_mutex;
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@ -544,7 +535,7 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
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if (r)
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goto error_pendings;
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r = amdgpu_cs_alloc_ib_local(dev, gpu_context, amdgpu_cs_ib_size_4K,
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r = amdgpu_cs_alloc_ib_local(gpu_context, amdgpu_cs_ib_size_4K,
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&gpu_context->fence_ib);
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if (r)
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goto error_fence_ib;
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@ -562,13 +553,13 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
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return 0;
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error_kernel:
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amdgpu_cs_free_ib(dev, gpu_context, gpu_context->fence_ib);
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amdgpu_cs_free_ib(gpu_context->fence_ib);
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error_fence_ib:
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amdgpu_cs_destroy_pendings(dev, gpu_context);
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amdgpu_cs_destroy_pendings(gpu_context);
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error_pendings:
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amdgpu_cs_destroy_ib_pool(dev, gpu_context);
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amdgpu_cs_destroy_ib_pool(gpu_context);
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error_pool:
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pthread_mutex_destroy(&gpu_context->sequence_mutex);
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@ -586,26 +577,23 @@ error_mutex:
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*
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* \return 0 on success otherwise POSIX Error code
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*/
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int amdgpu_cs_ctx_free(amdgpu_device_handle dev,
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amdgpu_context_handle context)
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int amdgpu_cs_ctx_free(amdgpu_context_handle context)
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{
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int r;
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union drm_amdgpu_ctx args;
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int r;
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if (NULL == dev)
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return -EINVAL;
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if (NULL == context)
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return -EINVAL;
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r = amdgpu_cs_free_ib(dev, context, context->fence_ib);
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r = amdgpu_cs_free_ib(context->fence_ib);
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if (r)
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return r;
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r = amdgpu_cs_destroy_pendings(dev, context);
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r = amdgpu_cs_destroy_pendings(context);
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if (r)
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return r;
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r = amdgpu_cs_destroy_ib_pool(dev, context);
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r = amdgpu_cs_destroy_ib_pool(context);
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if (r)
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return r;
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@ -615,15 +603,15 @@ int amdgpu_cs_ctx_free(amdgpu_device_handle dev,
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memset(&args, 0, sizeof(args));
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args.in.op = AMDGPU_CTX_OP_FREE_CTX;
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args.in.ctx_id = context->id;
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r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CTX, &args, sizeof(args));
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r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
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&args, sizeof(args));
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free(context);
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return r;
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}
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static int amdgpu_cs_create_bo_list(amdgpu_device_handle dev,
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amdgpu_context_handle context,
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static int amdgpu_cs_create_bo_list(amdgpu_context_handle context,
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struct amdgpu_cs_request *request,
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amdgpu_ib_handle fence_ib,
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uint32_t *handle)
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@ -663,7 +651,7 @@ static int amdgpu_cs_create_bo_list(amdgpu_device_handle dev,
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if (fence_ib)
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list[i].bo_handle = fence_ib->buf_handle->handle;
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r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST,
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r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_BO_LIST,
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&args, sizeof(args));
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if (r)
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return r;
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@ -672,7 +660,7 @@ static int amdgpu_cs_create_bo_list(amdgpu_device_handle dev,
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return 0;
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}
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static int amdgpu_cs_free_bo_list(amdgpu_device_handle dev, uint32_t handle)
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static int amdgpu_cs_free_bo_list(amdgpu_context_handle context, uint32_t handle)
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{
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union drm_amdgpu_bo_list args;
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int r;
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@ -684,7 +672,7 @@ static int amdgpu_cs_free_bo_list(amdgpu_device_handle dev, uint32_t handle)
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args.in.operation = AMDGPU_BO_LIST_OP_DESTROY;
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args.in.list_handle = handle;
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r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST,
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r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_BO_LIST,
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&args, sizeof(args));
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return r;
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@ -705,8 +693,7 @@ static uint32_t amdgpu_cs_fence_index(unsigned ip, unsigned ring)
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* \return 0 on success otherwise POSIX Error code
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* \sa amdgpu_cs_submit()
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*/
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static int amdgpu_cs_submit_one(amdgpu_device_handle dev,
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amdgpu_context_handle context,
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static int amdgpu_cs_submit_one(amdgpu_context_handle context,
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struct amdgpu_cs_request *ibs_request,
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uint64_t *fence)
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{
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@ -763,7 +750,7 @@ static int amdgpu_cs_submit_one(amdgpu_device_handle dev,
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chunk_data[i].ib_data.flags = AMDGPU_IB_FLAG_CE;
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}
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|
||||
r = amdgpu_cs_create_bo_list(dev, context, ibs_request, NULL,
|
||||
r = amdgpu_cs_create_bo_list(context, ibs_request, NULL,
|
||||
&bo_list_handle);
|
||||
if (r)
|
||||
goto error_unlock;
|
||||
|
|
@ -789,7 +776,7 @@ static int amdgpu_cs_submit_one(amdgpu_device_handle dev,
|
|||
chunk_data[i].fence_data.offset *= sizeof(uint64_t);
|
||||
}
|
||||
|
||||
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CS,
|
||||
r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CS,
|
||||
&cs, sizeof(cs));
|
||||
if (r)
|
||||
goto error_unlock;
|
||||
|
|
@ -816,7 +803,7 @@ static int amdgpu_cs_submit_one(amdgpu_device_handle dev,
|
|||
|
||||
pthread_mutex_unlock(&context->sequence_mutex);
|
||||
|
||||
r = amdgpu_cs_free_bo_list(dev, bo_list_handle);
|
||||
r = amdgpu_cs_free_bo_list(context, bo_list_handle);
|
||||
if (r)
|
||||
goto error_free;
|
||||
|
||||
|
|
@ -831,18 +818,15 @@ error_free:
|
|||
return r;
|
||||
}
|
||||
|
||||
int amdgpu_cs_submit(amdgpu_device_handle dev,
|
||||
amdgpu_context_handle context,
|
||||
int amdgpu_cs_submit(amdgpu_context_handle context,
|
||||
uint64_t flags,
|
||||
struct amdgpu_cs_request *ibs_request,
|
||||
uint32_t number_of_requests,
|
||||
uint64_t *fences)
|
||||
{
|
||||
int r;
|
||||
uint32_t i;
|
||||
int r;
|
||||
|
||||
if (NULL == dev)
|
||||
return -EINVAL;
|
||||
if (NULL == context)
|
||||
return -EINVAL;
|
||||
if (NULL == ibs_request)
|
||||
|
|
@ -852,7 +836,7 @@ int amdgpu_cs_submit(amdgpu_device_handle dev,
|
|||
|
||||
r = 0;
|
||||
for (i = 0; i < number_of_requests; i++) {
|
||||
r = amdgpu_cs_submit_one(dev, context, ibs_request, fences);
|
||||
r = amdgpu_cs_submit_one(context, ibs_request, fences);
|
||||
if (r)
|
||||
break;
|
||||
fences++;
|
||||
|
|
@ -915,8 +899,7 @@ static int amdgpu_ioctl_wait_cs(amdgpu_device_handle dev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
int amdgpu_cs_query_fence_status(amdgpu_device_handle dev,
|
||||
struct amdgpu_cs_query_fence *fence,
|
||||
int amdgpu_cs_query_fence_status(struct amdgpu_cs_query_fence *fence,
|
||||
uint32_t *expired)
|
||||
{
|
||||
amdgpu_context_handle context;
|
||||
|
|
@ -927,8 +910,6 @@ int amdgpu_cs_query_fence_status(amdgpu_device_handle dev,
|
|||
bool busy = true;
|
||||
int r;
|
||||
|
||||
if (NULL == dev)
|
||||
return -EINVAL;
|
||||
if (NULL == fence)
|
||||
return -EINVAL;
|
||||
if (NULL == expired)
|
||||
|
|
@ -969,7 +950,7 @@ int amdgpu_cs_query_fence_status(amdgpu_device_handle dev,
|
|||
|
||||
pthread_mutex_unlock(&context->sequence_mutex);
|
||||
|
||||
r = amdgpu_ioctl_wait_cs(dev, ip_type, ip_instance, ring,
|
||||
r = amdgpu_ioctl_wait_cs(context->dev, ip_type, ip_instance, ring,
|
||||
fence->fence, fence->timeout_ns, &busy);
|
||||
if (!r && !busy) {
|
||||
*expired = true;
|
||||
|
|
|
|||
|
|
@ -94,6 +94,7 @@ struct amdgpu_bo {
|
|||
* sequence_mutex -> pendings_mutex -> pool_mutex.
|
||||
*/
|
||||
struct amdgpu_context {
|
||||
struct amdgpu_device *dev;
|
||||
/** Mutex for accessing fences and to maintain command submissions
|
||||
and pending lists in good sequence. */
|
||||
pthread_mutex_t sequence_mutex;
|
||||
|
|
@ -116,6 +117,7 @@ struct amdgpu_context {
|
|||
};
|
||||
|
||||
struct amdgpu_ib {
|
||||
amdgpu_context_handle context;
|
||||
struct list_head list_node;
|
||||
amdgpu_bo_handle buf_handle;
|
||||
void *cpu;
|
||||
|
|
|
|||
|
|
@ -168,11 +168,11 @@ static void amdgpu_command_submission_gfx(void)
|
|||
r = amdgpu_cs_ctx_create(device_handle, &context_handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
r = amdgpu_cs_alloc_ib(device_handle, context_handle,
|
||||
r = amdgpu_cs_alloc_ib(context_handle,
|
||||
amdgpu_cs_ib_size_4K, &ib_result);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
r = amdgpu_cs_alloc_ib(device_handle, context_handle,
|
||||
r = amdgpu_cs_alloc_ib(context_handle,
|
||||
amdgpu_cs_ib_size_4K, &ib_result_ce);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
|
|
@ -199,7 +199,7 @@ static void amdgpu_command_submission_gfx(void)
|
|||
ibs_request.number_of_ibs = 2;
|
||||
ibs_request.ibs = ib_info;
|
||||
|
||||
r = amdgpu_cs_submit(device_handle, context_handle, 0,
|
||||
r = amdgpu_cs_submit(context_handle, 0,
|
||||
&ibs_request, 1, &fence_status.fence);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
|
|
@ -207,10 +207,10 @@ static void amdgpu_command_submission_gfx(void)
|
|||
fence_status.timeout_ns = AMDGPU_TIMEOUT_INFINITE;
|
||||
fence_status.ip_type = AMDGPU_HW_IP_GFX;
|
||||
|
||||
r = amdgpu_cs_query_fence_status(device_handle, &fence_status, &expired);
|
||||
r = amdgpu_cs_query_fence_status(&fence_status, &expired);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
r = amdgpu_cs_ctx_free(device_handle, context_handle);
|
||||
r = amdgpu_cs_ctx_free(context_handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
}
|
||||
|
||||
|
|
@ -230,7 +230,7 @@ static void amdgpu_command_submission_compute(void)
|
|||
|
||||
for (instance = 0; instance < 8; instance++) {
|
||||
memset(&ib_result, 0, sizeof(struct amdgpu_cs_ib_alloc_result));
|
||||
r = amdgpu_cs_alloc_ib(device_handle, context_handle,
|
||||
r = amdgpu_cs_alloc_ib(context_handle,
|
||||
amdgpu_cs_ib_size_4K, &ib_result);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
|
|
@ -249,7 +249,7 @@ static void amdgpu_command_submission_compute(void)
|
|||
ibs_request.ibs = &ib_info;
|
||||
|
||||
memset(&fence_status, 0, sizeof(struct amdgpu_cs_query_fence));
|
||||
r = amdgpu_cs_submit(device_handle, context_handle, 0,
|
||||
r = amdgpu_cs_submit(context_handle, 0,
|
||||
&ibs_request, 1, &fence_status.fence);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
|
|
@ -258,11 +258,11 @@ static void amdgpu_command_submission_compute(void)
|
|||
fence_status.ip_type = AMDGPU_HW_IP_COMPUTE;
|
||||
fence_status.ring = instance;
|
||||
|
||||
r = amdgpu_cs_query_fence_status(device_handle, &fence_status, &expired);
|
||||
r = amdgpu_cs_query_fence_status(&fence_status, &expired);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
}
|
||||
|
||||
r = amdgpu_cs_ctx_free(device_handle, context_handle);
|
||||
r = amdgpu_cs_ctx_free(context_handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
}
|
||||
|
||||
|
|
@ -291,7 +291,7 @@ static void amdgpu_sdma_test_exec_cs(amdgpu_context_handle context_handle,
|
|||
CU_ASSERT_TRUE(pm4_dw <= 1024);
|
||||
|
||||
/* allocate IB */
|
||||
r = amdgpu_cs_alloc_ib(device_handle, context_handle,
|
||||
r = amdgpu_cs_alloc_ib(context_handle,
|
||||
amdgpu_cs_ib_size_4K, &ib_result);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
|
|
@ -313,7 +313,7 @@ static void amdgpu_sdma_test_exec_cs(amdgpu_context_handle context_handle,
|
|||
CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
|
||||
|
||||
/* submit CS */
|
||||
r = amdgpu_cs_submit(device_handle, context_handle, 0,
|
||||
r = amdgpu_cs_submit(context_handle, 0,
|
||||
ibs_request, 1, &fence_status.fence);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
|
|
@ -323,8 +323,7 @@ static void amdgpu_sdma_test_exec_cs(amdgpu_context_handle context_handle,
|
|||
fence_status.timeout_ns = AMDGPU_TIMEOUT_INFINITE;
|
||||
|
||||
/* wait for IB accomplished */
|
||||
r = amdgpu_cs_query_fence_status(device_handle, &fence_status,
|
||||
&expired);
|
||||
r = amdgpu_cs_query_fence_status(&fence_status, &expired);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
CU_ASSERT_EQUAL(expired, true);
|
||||
}
|
||||
|
|
@ -408,7 +407,7 @@ static void amdgpu_command_submission_sdma_write_linear(void)
|
|||
free(pm4);
|
||||
|
||||
/* end of test */
|
||||
r = amdgpu_cs_ctx_free(device_handle, context_handle);
|
||||
r = amdgpu_cs_ctx_free(context_handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
}
|
||||
|
||||
|
|
@ -489,7 +488,7 @@ static void amdgpu_command_submission_sdma_const_fill(void)
|
|||
free(pm4);
|
||||
|
||||
/* end of test */
|
||||
r = amdgpu_cs_ctx_free(device_handle, context_handle);
|
||||
r = amdgpu_cs_ctx_free(context_handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
}
|
||||
|
||||
|
|
@ -590,7 +589,7 @@ static void amdgpu_command_submission_sdma_copy_linear(void)
|
|||
free(pm4);
|
||||
|
||||
/* end of test */
|
||||
r = amdgpu_cs_ctx_free(device_handle, context_handle);
|
||||
r = amdgpu_cs_ctx_free(context_handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
}
|
||||
|
||||
|
|
@ -664,6 +663,6 @@ static void amdgpu_userptr_test(void)
|
|||
CU_ASSERT_EQUAL(r, 0);
|
||||
free(ptr);
|
||||
|
||||
r = amdgpu_cs_ctx_free(device_handle, context_handle);
|
||||
r = amdgpu_cs_ctx_free(context_handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -73,8 +73,7 @@ int suite_cs_tests_init(void)
|
|||
if (r)
|
||||
return CUE_SINIT_FAILED;
|
||||
|
||||
r = amdgpu_cs_alloc_ib(device_handle, context_handle,
|
||||
IB_SIZE, &ib_result);
|
||||
r = amdgpu_cs_alloc_ib(context_handle, IB_SIZE, &ib_result);
|
||||
if (r)
|
||||
return CUE_SINIT_FAILED;
|
||||
|
||||
|
|
@ -88,11 +87,11 @@ int suite_cs_tests_clean(void)
|
|||
{
|
||||
int r;
|
||||
|
||||
r = amdgpu_cs_free_ib(device_handle, context_handle, ib_handle);
|
||||
r = amdgpu_cs_free_ib(ib_handle);
|
||||
if (r)
|
||||
return CUE_SCLEAN_FAILED;
|
||||
|
||||
r = amdgpu_cs_ctx_free(device_handle, context_handle);
|
||||
r = amdgpu_cs_ctx_free(context_handle);
|
||||
if (r)
|
||||
return CUE_SCLEAN_FAILED;
|
||||
|
||||
|
|
@ -121,13 +120,12 @@ static int submit(unsigned ndw, unsigned ip)
|
|||
ibs_request.number_of_ibs = 1;
|
||||
ibs_request.ibs = &ib_info;
|
||||
|
||||
r = amdgpu_cs_submit(device_handle, context_handle, 0,
|
||||
r = amdgpu_cs_submit(context_handle, 0,
|
||||
&ibs_request, 1, &fence_status.fence);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = amdgpu_cs_alloc_ib(device_handle, context_handle,
|
||||
IB_SIZE, &ib_result);
|
||||
r = amdgpu_cs_alloc_ib(context_handle, IB_SIZE, &ib_result);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
@ -138,7 +136,7 @@ static int submit(unsigned ndw, unsigned ip)
|
|||
fence_status.timeout_ns = AMDGPU_TIMEOUT_INFINITE;
|
||||
fence_status.ip_type = ip;
|
||||
|
||||
r = amdgpu_cs_query_fence_status(device_handle, &fence_status, &expired);
|
||||
r = amdgpu_cs_query_fence_status(&fence_status, &expired);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue