Add basic pgraph context for nv10.
It only fake a context switch : pgraph state are not save/restored.main
parent
4fe2858f53
commit
9d167f1f4b
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@ -89,6 +89,9 @@ struct nouveau_fifo
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struct mem_block *ramin_grctx;
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/* objects belonging to this fifo */
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struct nouveau_object *objs;
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/* XXX move this in PGRAPH struct */
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uint32_t pgraph_ctx_user;
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};
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struct nouveau_config {
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@ -488,6 +488,7 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init,
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init->channel = i;
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init->put_base = 0;
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dev_priv->cur_fifo = init->channel;
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dev_priv->fifos[i].pgraph_ctx_user = i << 24;
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nouveau_wait_for_idle(dev);
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@ -240,21 +240,32 @@ static void nouveau_nv04_context_switch(drm_device_t *dev)
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static void nouveau_nv10_context_switch(drm_device_t *dev)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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int channel;
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int channel, channel_old;
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channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1);
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/* 2-channel commute */
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// if (channel==0)
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// channel=1;
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// else
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// channel=0;
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// dev_priv->cur_fifo=channel;
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channel_old = (NV_READ(NV_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
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// NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000100);
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NV_WRITE(NV_PGRAPH_CTX_USER, NV_READ(NV_PGRAPH_CTX_USER)|0x1F000000);
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// NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
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/* touch PGRAPH_CTX_SWITCH* here ? */
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NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000100);
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DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel);
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NV_WRITE(NV_PGRAPH_FIFO,0x0);
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NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000);
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NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
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dev_priv->fifos[channel_old].pgraph_ctx_user = NV_READ(NV_PGRAPH_CTX_USER);
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//XXX save PGRAPH context
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NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000000);
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NV_WRITE(NV_PGRAPH_CTX_USER, dev_priv->fifos[channel].pgraph_ctx_user);
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//XXX restore PGRAPH context
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printk("ctx_user %x %x\n", dev_priv->fifos[channel_old].pgraph_ctx_user, dev_priv->fifos[channel].pgraph_ctx_user);
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NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
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NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10010100);
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NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001);
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NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001);
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NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
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NV_WRITE(NV_PGRAPH_FIFO,0x1);
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}
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static void nouveau_pgraph_irq_handler(drm_device_t *dev)
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