Possibly fix stanford checker complaints about sarea
Keith Whitwell
parent
fdf320a1b8
commit
9e7d6177d1
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@ -888,15 +888,14 @@ typedef struct {
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static void radeon_cp_dispatch_vertex( drm_device_t *dev,
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drm_buf_t *buf,
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drm_radeon_tcl_prim_t *prim,
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drm_clip_rect_t *boxes,
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int nbox )
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drm_radeon_tcl_prim_t *prim )
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_clip_rect_t box;
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drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
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int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start;
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int numverts = (int)prim->numverts;
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int nbox = sarea_priv->nbox;
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int i = 0;
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RING_LOCALS;
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@ -916,10 +915,8 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
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do {
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/* Emit the next cliprect */
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if ( i < nbox ) {
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if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) ))
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return;
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radeon_emit_clip_rect( dev_priv, &box );
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radeon_emit_clip_rect( dev_priv,
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&sarea_priv->boxes[i] );
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}
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/* Emit the vertex buffer rendering commands */
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@ -998,18 +995,17 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
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static void radeon_cp_dispatch_indices( drm_device_t *dev,
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drm_buf_t *elt_buf,
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drm_radeon_tcl_prim_t *prim,
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drm_clip_rect_t *boxes,
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int nbox )
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drm_radeon_tcl_prim_t *prim )
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_clip_rect_t box;
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drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
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int offset = dev_priv->agp_buffers_offset + prim->offset;
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u32 *data;
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int dwords;
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int i = 0;
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int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
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int count = (prim->finish - start) / sizeof(u16);
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int nbox = sarea_priv->nbox;
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DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
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prim->prim,
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@ -1048,12 +1044,9 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
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(count << RADEON_NUM_VERTICES_SHIFT) );
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do {
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if ( i < nbox ) {
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if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) ))
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return;
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radeon_emit_clip_rect( dev_priv, &box );
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}
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if ( i < nbox )
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radeon_emit_clip_rect( dev_priv,
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&sarea_priv->boxes[i] );
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radeon_cp_dispatch_indirect( dev, elt_buf,
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prim->start,
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@ -1453,9 +1446,7 @@ int radeon_cp_vertex( DRM_IOCTL_ARGS )
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prim.numverts = vertex.count;
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prim.vc_format = dev_priv->sarea_priv->vc_format;
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radeon_cp_dispatch_vertex( dev, buf, &prim,
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dev_priv->sarea_priv->boxes,
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dev_priv->sarea_priv->nbox );
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radeon_cp_dispatch_vertex( dev, buf, &prim );
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}
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if (vertex.discard) {
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@ -1553,9 +1544,7 @@ int radeon_cp_indices( DRM_IOCTL_ARGS )
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prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
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prim.vc_format = dev_priv->sarea_priv->vc_format;
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radeon_cp_dispatch_indices( dev, buf, &prim,
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dev_priv->sarea_priv->boxes,
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dev_priv->sarea_priv->nbox );
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radeon_cp_dispatch_indices( dev, buf, &prim );
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if (elts.discard) {
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radeon_cp_discard_buffer( dev, buf );
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}
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@ -1772,16 +1761,12 @@ int radeon_cp_vertex2( DRM_IOCTL_ARGS )
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tclprim.offset = prim.numverts * 64;
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tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
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radeon_cp_dispatch_indices( dev, buf, &tclprim,
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sarea_priv->boxes,
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sarea_priv->nbox);
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radeon_cp_dispatch_indices( dev, buf, &tclprim );
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} else {
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tclprim.numverts = prim.numverts;
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tclprim.offset = 0; /* not used */
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radeon_cp_dispatch_vertex( dev, buf, &tclprim,
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sarea_priv->boxes,
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sarea_priv->nbox);
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radeon_cp_dispatch_vertex( dev, buf, &tclprim );
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}
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if (sarea_priv->nbox == 1)
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@ -888,15 +888,14 @@ typedef struct {
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static void radeon_cp_dispatch_vertex( drm_device_t *dev,
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drm_buf_t *buf,
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drm_radeon_tcl_prim_t *prim,
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drm_clip_rect_t *boxes,
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int nbox )
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drm_radeon_tcl_prim_t *prim )
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_clip_rect_t box;
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drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
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int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start;
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int numverts = (int)prim->numverts;
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int nbox = sarea_priv->nbox;
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int i = 0;
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RING_LOCALS;
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@ -916,10 +915,8 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
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do {
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/* Emit the next cliprect */
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if ( i < nbox ) {
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if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) ))
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return;
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radeon_emit_clip_rect( dev_priv, &box );
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radeon_emit_clip_rect( dev_priv,
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&sarea_priv->boxes[i] );
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}
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/* Emit the vertex buffer rendering commands */
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@ -998,18 +995,17 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
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static void radeon_cp_dispatch_indices( drm_device_t *dev,
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drm_buf_t *elt_buf,
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drm_radeon_tcl_prim_t *prim,
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drm_clip_rect_t *boxes,
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int nbox )
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drm_radeon_tcl_prim_t *prim )
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_clip_rect_t box;
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drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
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int offset = dev_priv->agp_buffers_offset + prim->offset;
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u32 *data;
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int dwords;
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int i = 0;
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int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
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int count = (prim->finish - start) / sizeof(u16);
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int nbox = sarea_priv->nbox;
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DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
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prim->prim,
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@ -1048,12 +1044,9 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
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(count << RADEON_NUM_VERTICES_SHIFT) );
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do {
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if ( i < nbox ) {
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if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) ))
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return;
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radeon_emit_clip_rect( dev_priv, &box );
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}
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if ( i < nbox )
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radeon_emit_clip_rect( dev_priv,
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&sarea_priv->boxes[i] );
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radeon_cp_dispatch_indirect( dev, elt_buf,
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prim->start,
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@ -1453,9 +1446,7 @@ int radeon_cp_vertex( DRM_IOCTL_ARGS )
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prim.numverts = vertex.count;
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prim.vc_format = dev_priv->sarea_priv->vc_format;
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radeon_cp_dispatch_vertex( dev, buf, &prim,
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dev_priv->sarea_priv->boxes,
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dev_priv->sarea_priv->nbox );
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radeon_cp_dispatch_vertex( dev, buf, &prim );
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}
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if (vertex.discard) {
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@ -1553,9 +1544,7 @@ int radeon_cp_indices( DRM_IOCTL_ARGS )
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prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
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prim.vc_format = dev_priv->sarea_priv->vc_format;
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radeon_cp_dispatch_indices( dev, buf, &prim,
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dev_priv->sarea_priv->boxes,
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dev_priv->sarea_priv->nbox );
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radeon_cp_dispatch_indices( dev, buf, &prim );
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if (elts.discard) {
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radeon_cp_discard_buffer( dev, buf );
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}
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@ -1772,16 +1761,12 @@ int radeon_cp_vertex2( DRM_IOCTL_ARGS )
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tclprim.offset = prim.numverts * 64;
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tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
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radeon_cp_dispatch_indices( dev, buf, &tclprim,
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sarea_priv->boxes,
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sarea_priv->nbox);
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radeon_cp_dispatch_indices( dev, buf, &tclprim );
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} else {
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tclprim.numverts = prim.numverts;
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tclprim.offset = 0; /* not used */
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radeon_cp_dispatch_vertex( dev, buf, &tclprim,
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sarea_priv->boxes,
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sarea_priv->nbox);
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radeon_cp_dispatch_vertex( dev, buf, &tclprim );
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}
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if (sarea_priv->nbox == 1)
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